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364 lines
11 KiB
364 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2018-2019 SiFive, Inc. |
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* Wesley Terpstra |
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* Paul Walmsley |
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* |
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* This library supports configuration parsing and reprogramming of |
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* the CLN28HPC variant of the Analog Bits Wide Range PLL. The |
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* intention is for this library to be reusable for any device that |
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* integrates this PLL; thus the register structure and programming |
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* details are expected to be provided by a separate IP block driver. |
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* |
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* The bulk of this code is primarily useful for clock configurations |
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* that must operate at arbitrary rates, as opposed to clock configurations |
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* that are restricted by software or manufacturer guidance to a small, |
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* pre-determined set of performance points. |
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* |
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* References: |
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* - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01 |
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* - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset" |
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* https://static.dev.sifive.com/FU540-C000-v1.0.pdf |
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*/ |
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#include <linux/bug.h> |
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#include <linux/err.h> |
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#include <linux/log2.h> |
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#include <linux/math64.h> |
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#include <linux/clk/analogbits-wrpll-cln28hpc.h> |
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/* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */ |
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#define MIN_INPUT_FREQ 7000000 |
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/* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */ |
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#define MAX_INPUT_FREQ 600000000 |
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/* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */ |
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#define MIN_POST_DIVR_FREQ 7000000 |
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/* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */ |
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#define MAX_POST_DIVR_FREQ 200000000 |
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/* MIN_VCO_FREQ: minimum VCO frequency, in Hz (Fvco_min) */ |
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#define MIN_VCO_FREQ 2400000000UL |
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/* MAX_VCO_FREQ: maximum VCO frequency, in Hz (Fvco_max) */ |
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#define MAX_VCO_FREQ 4800000000ULL |
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/* MAX_DIVQ_DIVISOR: maximum output divisor. Selected by DIVQ = 6 */ |
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#define MAX_DIVQ_DIVISOR 64 |
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/* MAX_DIVR_DIVISOR: maximum reference divisor. Selected by DIVR = 63 */ |
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#define MAX_DIVR_DIVISOR 64 |
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/* MAX_LOCK_US: maximum PLL lock time, in microseconds (tLOCK_max) */ |
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#define MAX_LOCK_US 70 |
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/* |
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* ROUND_SHIFT: number of bits to shift to avoid precision loss in the rounding |
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* algorithm |
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*/ |
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#define ROUND_SHIFT 20 |
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/* |
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* Private functions |
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*/ |
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/** |
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* __wrpll_calc_filter_range() - determine PLL loop filter bandwidth |
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* @post_divr_freq: input clock rate after the R divider |
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* |
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* Select the value to be presented to the PLL RANGE input signals, based |
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* on the input clock frequency after the post-R-divider @post_divr_freq. |
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* This code follows the recommendations in the PLL datasheet for filter |
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* range selection. |
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* |
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* Return: The RANGE value to be presented to the PLL configuration inputs, |
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* or a negative return code upon error. |
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*/ |
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static int __wrpll_calc_filter_range(unsigned long post_divr_freq) |
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{ |
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if (post_divr_freq < MIN_POST_DIVR_FREQ || |
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post_divr_freq > MAX_POST_DIVR_FREQ) { |
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WARN(1, "%s: post-divider reference freq out of range: %lu", |
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__func__, post_divr_freq); |
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return -ERANGE; |
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} |
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switch (post_divr_freq) { |
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case 0 ... 10999999: |
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return 1; |
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case 11000000 ... 17999999: |
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return 2; |
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case 18000000 ... 29999999: |
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return 3; |
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case 30000000 ... 49999999: |
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return 4; |
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case 50000000 ... 79999999: |
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return 5; |
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case 80000000 ... 129999999: |
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return 6; |
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} |
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return 7; |
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} |
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/** |
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* __wrpll_calc_fbdiv() - return feedback fixed divide value |
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* @c: ptr to a struct wrpll_cfg record to read from |
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* |
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* The internal feedback path includes a fixed by-two divider; the |
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* external feedback path does not. Return the appropriate divider |
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* value (2 or 1) depending on whether internal or external feedback |
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* is enabled. This code doesn't test for invalid configurations |
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* (e.g. both or neither of WRPLL_FLAGS_*_FEEDBACK are set); it relies |
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* on the caller to do so. |
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* |
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* Context: Any context. Caller must protect the memory pointed to by |
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* @c from simultaneous modification. |
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* |
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* Return: 2 if internal feedback is enabled or 1 if external feedback |
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* is enabled. |
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*/ |
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static u8 __wrpll_calc_fbdiv(const struct wrpll_cfg *c) |
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{ |
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return (c->flags & WRPLL_FLAGS_INT_FEEDBACK_MASK) ? 2 : 1; |
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} |
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/** |
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* __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate |
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* @target_rate: target PLL output clock rate |
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* @vco_rate: pointer to a u64 to store the computed VCO rate into |
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* |
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* Determine a reasonable value for the PLL Q post-divider, based on the |
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* target output rate @target_rate for the PLL. Along with returning the |
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* computed Q divider value as the return value, this function stores the |
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* desired target VCO rate into the variable pointed to by @vco_rate. |
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* |
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* Context: Any context. Caller must protect the memory pointed to by |
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* @vco_rate from simultaneous access or modification. |
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* |
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* Return: a positive integer DIVQ value to be programmed into the hardware |
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* upon success, or 0 upon error (since 0 is an invalid DIVQ value) |
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*/ |
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static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate) |
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{ |
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u64 s; |
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u8 divq = 0; |
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if (!vco_rate) { |
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WARN_ON(1); |
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goto wcd_out; |
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} |
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s = div_u64(MAX_VCO_FREQ, target_rate); |
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if (s <= 1) { |
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divq = 1; |
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*vco_rate = MAX_VCO_FREQ; |
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} else if (s > MAX_DIVQ_DIVISOR) { |
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divq = ilog2(MAX_DIVQ_DIVISOR); |
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*vco_rate = MIN_VCO_FREQ; |
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} else { |
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divq = ilog2(s); |
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*vco_rate = (u64)target_rate << divq; |
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} |
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wcd_out: |
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return divq; |
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} |
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/** |
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* __wrpll_update_parent_rate() - update PLL data when parent rate changes |
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* @c: ptr to a struct wrpll_cfg record to write PLL data to |
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* @parent_rate: PLL input refclk rate (pre-R-divider) |
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* |
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* Pre-compute some data used by the PLL configuration algorithm when |
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* the PLL's reference clock rate changes. The intention is to avoid |
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* computation when the parent rate remains constant - expected to be |
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* the common case. |
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* |
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* Returns: 0 upon success or -ERANGE if the reference clock rate is |
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* out of range. |
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*/ |
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static int __wrpll_update_parent_rate(struct wrpll_cfg *c, |
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unsigned long parent_rate) |
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{ |
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u8 max_r_for_parent; |
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if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ) |
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return -ERANGE; |
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c->parent_rate = parent_rate; |
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max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ); |
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c->max_r = min_t(u8, MAX_DIVR_DIVISOR, max_r_for_parent); |
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c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ); |
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return 0; |
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} |
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/** |
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* wrpll_configure() - compute PLL configuration for a target rate |
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* @c: ptr to a struct wrpll_cfg record to write into |
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* @target_rate: target PLL output clock rate (post-Q-divider) |
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* @parent_rate: PLL input refclk rate (pre-R-divider) |
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* |
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* Compute the appropriate PLL signal configuration values and store |
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* in PLL context @c. PLL reprogramming is not glitchless, so the |
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* caller should switch any downstream logic to a different clock |
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* source or clock-gate it before presenting these values to the PLL |
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* configuration signals. |
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* |
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* The caller must pass this function a pre-initialized struct |
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* wrpll_cfg record: either initialized to zero (with the |
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* exception of the .name and .flags fields) or read from the PLL. |
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* |
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* Context: Any context. Caller must protect the memory pointed to by @c |
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* from simultaneous access or modification. |
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* |
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* Return: 0 upon success; anything else upon failure. |
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*/ |
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int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate, |
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unsigned long parent_rate) |
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{ |
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unsigned long ratio; |
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u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; |
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u32 best_f, f, post_divr_freq; |
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u8 fbdiv, divq, best_r, r; |
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int range; |
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if (c->flags == 0) { |
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WARN(1, "%s called with uninitialized PLL config", __func__); |
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return -EINVAL; |
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} |
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/* Initialize rounding data if it hasn't been initialized already */ |
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if (parent_rate != c->parent_rate) { |
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if (__wrpll_update_parent_rate(c, parent_rate)) { |
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pr_err("%s: PLL input rate is out of range\n", |
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__func__); |
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return -ERANGE; |
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} |
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} |
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c->flags &= ~WRPLL_FLAGS_RESET_MASK; |
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/* Put the PLL into bypass if the user requests the parent clock rate */ |
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if (target_rate == parent_rate) { |
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c->flags |= WRPLL_FLAGS_BYPASS_MASK; |
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return 0; |
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} |
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c->flags &= ~WRPLL_FLAGS_BYPASS_MASK; |
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/* Calculate the Q shift and target VCO rate */ |
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divq = __wrpll_calc_divq(target_rate, &target_vco_rate); |
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if (!divq) |
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return -1; |
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c->divq = divq; |
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/* Precalculate the pre-Q divider target ratio */ |
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ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate); |
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fbdiv = __wrpll_calc_fbdiv(c); |
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best_r = 0; |
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best_f = 0; |
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best_delta = MAX_VCO_FREQ; |
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/* |
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* Consider all values for R which land within |
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* [MIN_POST_DIVR_FREQ, MAX_POST_DIVR_FREQ]; prefer smaller R |
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*/ |
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for (r = c->init_r; r <= c->max_r; ++r) { |
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f_pre_div = ratio * r; |
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f = (f_pre_div + (1 << ROUND_SHIFT)) >> ROUND_SHIFT; |
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f >>= (fbdiv - 1); |
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post_divr_freq = div_u64(parent_rate, r); |
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vco_pre = fbdiv * post_divr_freq; |
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vco = vco_pre * f; |
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/* Ensure rounding didn't take us out of range */ |
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if (vco > target_vco_rate) { |
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--f; |
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vco = vco_pre * f; |
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} else if (vco < MIN_VCO_FREQ) { |
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++f; |
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vco = vco_pre * f; |
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} |
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delta = abs(target_rate - vco); |
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if (delta < best_delta) { |
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best_delta = delta; |
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best_r = r; |
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best_f = f; |
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} |
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} |
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c->divr = best_r - 1; |
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c->divf = best_f - 1; |
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post_divr_freq = div_u64(parent_rate, best_r); |
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/* Pick the best PLL jitter filter */ |
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range = __wrpll_calc_filter_range(post_divr_freq); |
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if (range < 0) |
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return range; |
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c->range = range; |
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return 0; |
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} |
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/** |
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* wrpll_calc_output_rate() - calculate the PLL's target output rate |
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* @c: ptr to a struct wrpll_cfg record to read from |
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* @parent_rate: PLL refclk rate |
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* |
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* Given a pointer to the PLL's current input configuration @c and the |
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* PLL's input reference clock rate @parent_rate (before the R |
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* pre-divider), calculate the PLL's output clock rate (after the Q |
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* post-divider). |
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* |
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* Context: Any context. Caller must protect the memory pointed to by @c |
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* from simultaneous modification. |
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* |
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* Return: the PLL's output clock rate, in Hz. The return value from |
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* this function is intended to be convenient to pass directly |
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* to the Linux clock framework; thus there is no explicit |
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* error return value. |
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*/ |
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unsigned long wrpll_calc_output_rate(const struct wrpll_cfg *c, |
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unsigned long parent_rate) |
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{ |
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u8 fbdiv; |
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u64 n; |
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if (c->flags & WRPLL_FLAGS_EXT_FEEDBACK_MASK) { |
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WARN(1, "external feedback mode not yet supported"); |
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return ULONG_MAX; |
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} |
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fbdiv = __wrpll_calc_fbdiv(c); |
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n = parent_rate * fbdiv * (c->divf + 1); |
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n = div_u64(n, c->divr + 1); |
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n >>= c->divq; |
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return n; |
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} |
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/** |
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* wrpll_calc_max_lock_us() - return the time for the PLL to lock |
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* @c: ptr to a struct wrpll_cfg record to read from |
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* |
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* Return the minimum amount of time (in microseconds) that the caller |
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* must wait after reprogramming the PLL to ensure that it is locked |
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* to the input frequency and stable. This is likely to depend on the DIVR |
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* value; this is under discussion with the manufacturer. |
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* |
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* Return: the minimum amount of time the caller must wait for the PLL |
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* to lock (in microseconds) |
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*/ |
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unsigned int wrpll_calc_max_lock_us(const struct wrpll_cfg *c) |
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{ |
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return MAX_LOCK_US; |
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}
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