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194 lines
4.2 KiB
194 lines
4.2 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// OWL pll clock driver |
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// |
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// Copyright (c) 2014 Actions Semi Inc. |
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// Author: David Liu <[email protected]> |
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// |
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// Copyright (c) 2018 Linaro Ltd. |
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// Author: Manivannan Sadhasivam <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include "owl-pll.h" |
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static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) |
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{ |
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u32 mul; |
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mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); |
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if (mul < pll_hw->min_mul) |
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mul = pll_hw->min_mul; |
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else if (mul > pll_hw->max_mul) |
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mul = pll_hw->max_mul; |
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return mul &= mul_mask(pll_hw); |
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} |
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static unsigned long _get_table_rate(const struct clk_pll_table *table, |
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unsigned int val) |
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{ |
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const struct clk_pll_table *clkt; |
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for (clkt = table; clkt->rate; clkt++) |
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if (clkt->val == val) |
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return clkt->rate; |
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return 0; |
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} |
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static const struct clk_pll_table *_get_pll_table( |
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const struct clk_pll_table *table, unsigned long rate) |
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{ |
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const struct clk_pll_table *clkt; |
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for (clkt = table; clkt->rate; clkt++) { |
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if (clkt->rate == rate) { |
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table = clkt; |
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break; |
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} else if (clkt->rate < rate) |
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table = clkt; |
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} |
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return table; |
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} |
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static long owl_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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struct owl_pll_hw *pll_hw = &pll->pll_hw; |
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const struct clk_pll_table *clkt; |
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u32 mul; |
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if (pll_hw->table) { |
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clkt = _get_pll_table(pll_hw->table, rate); |
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return clkt->rate; |
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} |
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/* fixed frequency */ |
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if (pll_hw->width == 0) |
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return pll_hw->bfreq; |
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mul = owl_pll_calculate_mul(pll_hw, rate); |
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return pll_hw->bfreq * mul; |
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} |
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static unsigned long owl_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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struct owl_pll_hw *pll_hw = &pll->pll_hw; |
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const struct owl_clk_common *common = &pll->common; |
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u32 val; |
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if (pll_hw->table) { |
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regmap_read(common->regmap, pll_hw->reg, &val); |
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val = val >> pll_hw->shift; |
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val &= mul_mask(pll_hw); |
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return _get_table_rate(pll_hw->table, val); |
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} |
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/* fixed frequency */ |
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if (pll_hw->width == 0) |
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return pll_hw->bfreq; |
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regmap_read(common->regmap, pll_hw->reg, &val); |
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val = val >> pll_hw->shift; |
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val &= mul_mask(pll_hw); |
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return pll_hw->bfreq * val; |
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} |
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static int owl_pll_is_enabled(struct clk_hw *hw) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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struct owl_pll_hw *pll_hw = &pll->pll_hw; |
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const struct owl_clk_common *common = &pll->common; |
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u32 reg; |
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regmap_read(common->regmap, pll_hw->reg, ®); |
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return !!(reg & BIT(pll_hw->bit_idx)); |
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} |
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static void owl_pll_set(const struct owl_clk_common *common, |
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const struct owl_pll_hw *pll_hw, bool enable) |
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{ |
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u32 reg; |
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regmap_read(common->regmap, pll_hw->reg, ®); |
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if (enable) |
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reg |= BIT(pll_hw->bit_idx); |
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else |
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reg &= ~BIT(pll_hw->bit_idx); |
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regmap_write(common->regmap, pll_hw->reg, reg); |
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} |
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static int owl_pll_enable(struct clk_hw *hw) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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const struct owl_clk_common *common = &pll->common; |
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owl_pll_set(common, &pll->pll_hw, true); |
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return 0; |
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} |
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static void owl_pll_disable(struct clk_hw *hw) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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const struct owl_clk_common *common = &pll->common; |
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owl_pll_set(common, &pll->pll_hw, false); |
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} |
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static int owl_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct owl_pll *pll = hw_to_owl_pll(hw); |
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struct owl_pll_hw *pll_hw = &pll->pll_hw; |
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const struct owl_clk_common *common = &pll->common; |
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const struct clk_pll_table *clkt; |
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u32 val, reg; |
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/* fixed frequency */ |
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if (pll_hw->width == 0) |
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return 0; |
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if (pll_hw->table) { |
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clkt = _get_pll_table(pll_hw->table, rate); |
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val = clkt->val; |
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} else { |
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val = owl_pll_calculate_mul(pll_hw, rate); |
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} |
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regmap_read(common->regmap, pll_hw->reg, ®); |
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reg &= ~mul_mask(pll_hw); |
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reg |= val << pll_hw->shift; |
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regmap_write(common->regmap, pll_hw->reg, reg); |
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udelay(pll_hw->delay); |
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return 0; |
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} |
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const struct clk_ops owl_pll_ops = { |
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.enable = owl_pll_enable, |
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.disable = owl_pll_disable, |
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.is_enabled = owl_pll_is_enabled, |
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.round_rate = owl_pll_round_rate, |
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.recalc_rate = owl_pll_recalc_rate, |
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.set_rate = owl_pll_set_rate, |
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};
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