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77 lines
1.7 KiB
77 lines
1.7 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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// |
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// OWL gate clock driver |
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// |
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// Copyright (c) 2014 Actions Semi Inc. |
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// Author: David Liu <[email protected]> |
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// |
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// Copyright (c) 2018 Linaro Ltd. |
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// Author: Manivannan Sadhasivam <[email protected]> |
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#include <linux/clk-provider.h> |
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#include <linux/regmap.h> |
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#include "owl-gate.h" |
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void owl_gate_set(const struct owl_clk_common *common, |
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const struct owl_gate_hw *gate_hw, bool enable) |
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{ |
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int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; |
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u32 reg; |
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set ^= enable; |
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regmap_read(common->regmap, gate_hw->reg, ®); |
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if (set) |
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reg |= BIT(gate_hw->bit_idx); |
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else |
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reg &= ~BIT(gate_hw->bit_idx); |
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regmap_write(common->regmap, gate_hw->reg, reg); |
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} |
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static void owl_gate_disable(struct clk_hw *hw) |
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{ |
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struct owl_gate *gate = hw_to_owl_gate(hw); |
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struct owl_clk_common *common = &gate->common; |
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owl_gate_set(common, &gate->gate_hw, false); |
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} |
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static int owl_gate_enable(struct clk_hw *hw) |
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{ |
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struct owl_gate *gate = hw_to_owl_gate(hw); |
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struct owl_clk_common *common = &gate->common; |
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owl_gate_set(common, &gate->gate_hw, true); |
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return 0; |
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} |
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int owl_gate_clk_is_enabled(const struct owl_clk_common *common, |
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const struct owl_gate_hw *gate_hw) |
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{ |
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u32 reg; |
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regmap_read(common->regmap, gate_hw->reg, ®); |
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if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE) |
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reg ^= BIT(gate_hw->bit_idx); |
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return !!(reg & BIT(gate_hw->bit_idx)); |
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} |
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static int owl_gate_is_enabled(struct clk_hw *hw) |
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{ |
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struct owl_gate *gate = hw_to_owl_gate(hw); |
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struct owl_clk_common *common = &gate->common; |
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return owl_gate_clk_is_enabled(common, &gate->gate_hw); |
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} |
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const struct clk_ops owl_gate_ops = { |
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.disable = owl_gate_disable, |
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.enable = owl_gate_enable, |
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.is_enabled = owl_gate_is_enabled, |
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};
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