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213 lines
5.7 KiB
213 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPC8272 ADS board support |
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* |
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* Copyright 2007 Freescale Semiconductor, Inc. |
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* Author: Scott Wood <[email protected]> |
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* |
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* Based on code by Vitaly Bordug <[email protected]> |
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* Copyright (c) 2006 MontaVista Software, Inc. |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/fsl_devices.h> |
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#include <linux/of_address.h> |
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#include <linux/of_fdt.h> |
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#include <linux/of_platform.h> |
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#include <linux/io.h> |
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#include <asm/cpm2.h> |
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#include <asm/udbg.h> |
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#include <asm/machdep.h> |
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#include <asm/time.h> |
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#include <platforms/82xx/pq2.h> |
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#include <sysdev/fsl_soc.h> |
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#include <sysdev/cpm2_pic.h> |
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#include "pq2.h" |
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static void __init mpc8272_ads_pic_init(void) |
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{ |
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struct device_node *np = of_find_compatible_node(NULL, NULL, |
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"fsl,cpm2-pic"); |
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if (!np) { |
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printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n"); |
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return; |
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} |
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cpm2_pic_init(np); |
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of_node_put(np); |
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/* Initialize stuff for the 82xx CPLD IC and install demux */ |
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pq2ads_pci_init_irq(); |
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} |
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struct cpm_pin { |
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int port, pin, flags; |
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}; |
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static struct cpm_pin mpc8272_ads_pins[] = { |
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/* SCC1 */ |
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{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, |
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{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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/* SCC4 */ |
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{3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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/* FCC1 */ |
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{0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, |
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{0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, |
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{0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, |
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{0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, |
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{0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, |
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{0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, |
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{2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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/* FCC2 */ |
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{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY}, |
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{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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/* I2C */ |
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{3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, |
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{3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN}, |
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/* USB */ |
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{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, |
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{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, |
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}; |
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static void __init init_ioports(void) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) { |
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struct cpm_pin *pin = &mpc8272_ads_pins[i]; |
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cpm2_set_pin(pin->port, pin->pin, pin->flags); |
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} |
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX); |
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX); |
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cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX); |
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cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); |
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cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX); |
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cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX); |
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cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX); |
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cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX); |
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX); |
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX); |
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} |
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static void __init mpc8272_ads_setup_arch(void) |
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{ |
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struct device_node *np; |
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__be32 __iomem *bcsr; |
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if (ppc_md.progress) |
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ppc_md.progress("mpc8272_ads_setup_arch()", 0); |
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cpm2_reset(); |
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr"); |
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if (!np) { |
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printk(KERN_ERR "No bcsr in device tree\n"); |
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return; |
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} |
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bcsr = of_iomap(np, 0); |
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of_node_put(np); |
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if (!bcsr) { |
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printk(KERN_ERR "Cannot map BCSR registers\n"); |
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return; |
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} |
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#define BCSR1_FETHIEN 0x08000000 |
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#define BCSR1_FETH_RST 0x04000000 |
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#define BCSR1_RS232_EN1 0x02000000 |
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#define BCSR1_RS232_EN2 0x01000000 |
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#define BCSR3_USB_nEN 0x80000000 |
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#define BCSR3_FETHIEN2 0x10000000 |
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#define BCSR3_FETH2_RST 0x08000000 |
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clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN); |
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setbits32(&bcsr[1], BCSR1_FETH_RST); |
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clrbits32(&bcsr[3], BCSR3_FETHIEN2); |
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setbits32(&bcsr[3], BCSR3_FETH2_RST); |
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clrbits32(&bcsr[3], BCSR3_USB_nEN); |
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iounmap(bcsr); |
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init_ioports(); |
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if (ppc_md.progress) |
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ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0); |
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} |
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static const struct of_device_id of_bus_ids[] __initconst = { |
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{ .name = "soc", }, |
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{ .name = "cpm", }, |
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{ .name = "localbus", }, |
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{}, |
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}; |
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static int __init declare_of_platform_devices(void) |
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{ |
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/* Publish the QE devices */ |
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of_platform_bus_probe(NULL, of_bus_ids, NULL); |
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return 0; |
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} |
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machine_device_initcall(mpc8272_ads, declare_of_platform_devices); |
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/* |
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* Called very early, device-tree isn't unflattened |
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*/ |
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static int __init mpc8272_ads_probe(void) |
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{ |
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return of_machine_is_compatible("fsl,mpc8272ads"); |
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} |
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define_machine(mpc8272_ads) |
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{ |
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.name = "Freescale MPC8272 ADS", |
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.probe = mpc8272_ads_probe, |
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.setup_arch = mpc8272_ads_setup_arch, |
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.discover_phbs = pq2_init_pci, |
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.init_IRQ = mpc8272_ads_pic_init, |
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.get_irq = cpm2_get_irq, |
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.calibrate_decr = generic_calibrate_decr, |
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.restart = pq2_restart, |
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.progress = udbg_progress, |
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};
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