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204 lines
5.3 KiB
204 lines
5.3 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/init.h> |
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#include <linux/suspend.h> |
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#include <linux/io.h> |
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#include <asm/time.h> |
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#include <asm/cacheflush.h> |
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#include <asm/mpc52xx.h> |
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/* these are defined in mpc52xx_sleep.S, and only used here */ |
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extern void mpc52xx_deep_sleep(void __iomem *sram, void __iomem *sdram_regs, |
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struct mpc52xx_cdm __iomem *, struct mpc52xx_intr __iomem*); |
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extern void mpc52xx_ds_sram(void); |
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extern const long mpc52xx_ds_sram_size; |
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extern void mpc52xx_ds_cached(void); |
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extern const long mpc52xx_ds_cached_size; |
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static void __iomem *mbar; |
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static void __iomem *sdram; |
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static struct mpc52xx_cdm __iomem *cdm; |
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static struct mpc52xx_intr __iomem *intr; |
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static struct mpc52xx_gpio_wkup __iomem *gpiow; |
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static void __iomem *sram; |
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static int sram_size; |
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struct mpc52xx_suspend mpc52xx_suspend; |
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static int mpc52xx_pm_valid(suspend_state_t state) |
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{ |
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switch (state) { |
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case PM_SUSPEND_STANDBY: |
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return 1; |
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default: |
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return 0; |
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} |
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} |
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int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) |
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{ |
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u16 tmp; |
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/* enable gpio */ |
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out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); |
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/* set as input */ |
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out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); |
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/* enable deep sleep interrupt */ |
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out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); |
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/* low/high level creates wakeup interrupt */ |
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tmp = in_be16(&gpiow->wkup_itype); |
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tmp &= ~(0x3 << (pin * 2)); |
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tmp |= (!level + 1) << (pin * 2); |
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out_be16(&gpiow->wkup_itype, tmp); |
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/* master enable */ |
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out_8(&gpiow->wkup_maste, 1); |
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return 0; |
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} |
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int mpc52xx_pm_prepare(void) |
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{ |
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struct device_node *np; |
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const struct of_device_id immr_ids[] = { |
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{ .compatible = "fsl,mpc5200-immr", }, |
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{ .compatible = "fsl,mpc5200b-immr", }, |
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{ .type = "soc", .compatible = "mpc5200", }, /* lite5200 */ |
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{ .type = "builtin", .compatible = "mpc5200", }, /* efika */ |
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{} |
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}; |
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struct resource res; |
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/* map the whole register space */ |
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np = of_find_matching_node(NULL, immr_ids); |
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if (of_address_to_resource(np, 0, &res)) { |
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pr_err("mpc52xx_pm_prepare(): could not get IMMR address\n"); |
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of_node_put(np); |
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return -ENOSYS; |
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} |
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mbar = ioremap(res.start, 0xc000); /* we should map whole region including SRAM */ |
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of_node_put(np); |
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if (!mbar) { |
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pr_err("mpc52xx_pm_prepare(): could not map registers\n"); |
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return -ENOSYS; |
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} |
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/* these offsets are from mpc5200 users manual */ |
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sdram = mbar + 0x100; |
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cdm = mbar + 0x200; |
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intr = mbar + 0x500; |
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gpiow = mbar + 0xc00; |
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sram = mbar + 0x8000; /* Those will be handled by the */ |
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sram_size = 0x4000; /* bestcomm driver soon */ |
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/* call board suspend code, if applicable */ |
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if (mpc52xx_suspend.board_suspend_prepare) |
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mpc52xx_suspend.board_suspend_prepare(mbar); |
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else { |
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printk(KERN_ALERT "%s: %i don't know how to wake up the board\n", |
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__func__, __LINE__); |
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goto out_unmap; |
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} |
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return 0; |
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out_unmap: |
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iounmap(mbar); |
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return -ENOSYS; |
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} |
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char saved_sram[0x4000]; |
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int mpc52xx_pm_enter(suspend_state_t state) |
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{ |
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u32 clk_enables; |
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u32 msr, hid0; |
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u32 intr_main_mask; |
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void __iomem * irq_0x500 = (void __iomem *)CONFIG_KERNEL_START + 0x500; |
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unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size; |
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char saved_0x500[0x600-0x500]; |
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if (WARN_ON(mpc52xx_ds_cached_size > sizeof(saved_0x500))) |
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return -ENOMEM; |
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/* disable all interrupts in PIC */ |
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intr_main_mask = in_be32(&intr->main_mask); |
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out_be32(&intr->main_mask, intr_main_mask | 0x1ffff); |
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/* don't let DEC expire any time soon */ |
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mtspr(SPRN_DEC, 0x7fffffff); |
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/* save SRAM */ |
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memcpy(saved_sram, sram, sram_size); |
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/* copy low level suspend code to sram */ |
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memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size); |
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out_8(&cdm->ccs_sleep_enable, 1); |
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out_8(&cdm->osc_sleep_enable, 1); |
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out_8(&cdm->ccs_qreq_test, 1); |
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/* disable all but SDRAM and bestcomm (SRAM) clocks */ |
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clk_enables = in_be32(&cdm->clk_enables); |
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out_be32(&cdm->clk_enables, clk_enables & 0x00088000); |
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/* disable power management */ |
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msr = mfmsr(); |
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mtmsr(msr & ~MSR_POW); |
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/* enable sleep mode, disable others */ |
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hid0 = mfspr(SPRN_HID0); |
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mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP); |
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/* save original, copy our irq handler, flush from dcache and invalidate icache */ |
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memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size); |
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memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size); |
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flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); |
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/* call low-level sleep code */ |
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mpc52xx_deep_sleep(sram, sdram, cdm, intr); |
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/* restore original irq handler */ |
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memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size); |
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flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop); |
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/* restore old power mode */ |
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mtmsr(msr & ~MSR_POW); |
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mtspr(SPRN_HID0, hid0); |
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mtmsr(msr); |
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out_be32(&cdm->clk_enables, clk_enables); |
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out_8(&cdm->ccs_sleep_enable, 0); |
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out_8(&cdm->osc_sleep_enable, 0); |
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/* restore SRAM */ |
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memcpy(sram, saved_sram, sram_size); |
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/* reenable interrupts in PIC */ |
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out_be32(&intr->main_mask, intr_main_mask); |
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return 0; |
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} |
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void mpc52xx_pm_finish(void) |
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{ |
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/* call board resume code */ |
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if (mpc52xx_suspend.board_resume_finish) |
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mpc52xx_suspend.board_resume_finish(mbar); |
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iounmap(mbar); |
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} |
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static const struct platform_suspend_ops mpc52xx_pm_ops = { |
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.valid = mpc52xx_pm_valid, |
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.prepare = mpc52xx_pm_prepare, |
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.enter = mpc52xx_pm_enter, |
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.finish = mpc52xx_pm_finish, |
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}; |
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int __init mpc52xx_pm_init(void) |
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{ |
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suspend_set_ops(&mpc52xx_pm_ops); |
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return 0; |
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}
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