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1219 lines
31 KiB
1219 lines
31 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* |
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* Common boot and setup code. |
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* |
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* Copyright (C) 2001 PPC64 Team, IBM Corp |
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*/ |
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|
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#include <linux/export.h> |
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#include <linux/string.h> |
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#include <linux/sched.h> |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/reboot.h> |
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#include <linux/delay.h> |
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#include <linux/initrd.h> |
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#include <linux/seq_file.h> |
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#include <linux/ioport.h> |
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#include <linux/console.h> |
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#include <linux/utsname.h> |
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#include <linux/tty.h> |
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#include <linux/root_dev.h> |
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#include <linux/notifier.h> |
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#include <linux/cpu.h> |
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#include <linux/unistd.h> |
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#include <linux/serial.h> |
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#include <linux/serial_8250.h> |
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#include <linux/memblock.h> |
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#include <linux/pci.h> |
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#include <linux/lockdep.h> |
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#include <linux/memory.h> |
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#include <linux/nmi.h> |
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#include <linux/pgtable.h> |
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#include <asm/debugfs.h> |
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#include <asm/io.h> |
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#include <asm/kdump.h> |
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#include <asm/prom.h> |
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#include <asm/processor.h> |
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#include <asm/smp.h> |
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#include <asm/elf.h> |
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#include <asm/machdep.h> |
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#include <asm/paca.h> |
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#include <asm/time.h> |
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#include <asm/cputable.h> |
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#include <asm/dt_cpu_ftrs.h> |
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#include <asm/sections.h> |
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#include <asm/btext.h> |
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#include <asm/nvram.h> |
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#include <asm/setup.h> |
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#include <asm/rtas.h> |
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#include <asm/iommu.h> |
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#include <asm/serial.h> |
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#include <asm/cache.h> |
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#include <asm/page.h> |
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#include <asm/mmu.h> |
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#include <asm/firmware.h> |
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#include <asm/xmon.h> |
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#include <asm/udbg.h> |
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#include <asm/kexec.h> |
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#include <asm/code-patching.h> |
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#include <asm/livepatch.h> |
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#include <asm/opal.h> |
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#include <asm/cputhreads.h> |
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#include <asm/hw_irq.h> |
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#include <asm/feature-fixups.h> |
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#include <asm/kup.h> |
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#include <asm/early_ioremap.h> |
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#include <asm/pgalloc.h> |
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#include <asm/asm-prototypes.h> |
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#include "setup.h" |
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int spinning_secondaries; |
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u64 ppc64_pft_size; |
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struct ppc64_caches ppc64_caches = { |
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.l1d = { |
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.block_size = 0x40, |
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.log_block_size = 6, |
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}, |
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.l1i = { |
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.block_size = 0x40, |
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.log_block_size = 6 |
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}, |
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}; |
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EXPORT_SYMBOL_GPL(ppc64_caches); |
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#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP) |
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void __init setup_tlb_core_data(void) |
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{ |
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int cpu; |
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BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0); |
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for_each_possible_cpu(cpu) { |
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int first = cpu_first_thread_sibling(cpu); |
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/* |
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* If we boot via kdump on a non-primary thread, |
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* make sure we point at the thread that actually |
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* set up this TLB. |
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*/ |
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if (cpu_first_thread_sibling(boot_cpuid) == first) |
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first = boot_cpuid; |
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paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd; |
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/* |
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* If we have threads, we need either tlbsrx. |
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* or e6500 tablewalk mode, or else TLB handlers |
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* will be racy and could produce duplicate entries. |
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* Should we panic instead? |
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*/ |
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WARN_ONCE(smt_enabled_at_boot >= 2 && |
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!mmu_has_feature(MMU_FTR_USE_TLBRSRV) && |
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book3e_htw_mode != PPC_HTW_E6500, |
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"%s: unsupported MMU configuration\n", __func__); |
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} |
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} |
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#endif |
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#ifdef CONFIG_SMP |
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static char *smt_enabled_cmdline; |
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/* Look for ibm,smt-enabled OF option */ |
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void __init check_smt_enabled(void) |
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{ |
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struct device_node *dn; |
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const char *smt_option; |
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|
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/* Default to enabling all threads */ |
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smt_enabled_at_boot = threads_per_core; |
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|
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/* Allow the command line to overrule the OF option */ |
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if (smt_enabled_cmdline) { |
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if (!strcmp(smt_enabled_cmdline, "on")) |
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smt_enabled_at_boot = threads_per_core; |
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else if (!strcmp(smt_enabled_cmdline, "off")) |
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smt_enabled_at_boot = 0; |
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else { |
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int smt; |
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int rc; |
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rc = kstrtoint(smt_enabled_cmdline, 10, &smt); |
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if (!rc) |
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smt_enabled_at_boot = |
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min(threads_per_core, smt); |
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} |
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} else { |
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dn = of_find_node_by_path("/options"); |
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if (dn) { |
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smt_option = of_get_property(dn, "ibm,smt-enabled", |
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NULL); |
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if (smt_option) { |
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if (!strcmp(smt_option, "on")) |
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smt_enabled_at_boot = threads_per_core; |
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else if (!strcmp(smt_option, "off")) |
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smt_enabled_at_boot = 0; |
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} |
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of_node_put(dn); |
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} |
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} |
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} |
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/* Look for smt-enabled= cmdline option */ |
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static int __init early_smt_enabled(char *p) |
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{ |
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smt_enabled_cmdline = p; |
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return 0; |
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} |
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early_param("smt-enabled", early_smt_enabled); |
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#endif /* CONFIG_SMP */ |
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/** Fix up paca fields required for the boot cpu */ |
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static void __init fixup_boot_paca(void) |
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{ |
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/* The boot cpu is started */ |
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get_paca()->cpu_start = 1; |
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/* Allow percpu accesses to work until we setup percpu data */ |
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get_paca()->data_offset = 0; |
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/* Mark interrupts disabled in PACA */ |
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irq_soft_mask_set(IRQS_DISABLED); |
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} |
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static void __init configure_exceptions(void) |
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{ |
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/* |
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* Setup the trampolines from the lowmem exception vectors |
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* to the kdump kernel when not using a relocatable kernel. |
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*/ |
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setup_kdump_trampoline(); |
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/* Under a PAPR hypervisor, we need hypercalls */ |
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if (firmware_has_feature(FW_FEATURE_SET_MODE)) { |
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/* Enable AIL if possible */ |
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if (!pseries_enable_reloc_on_exc()) { |
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init_task.thread.fscr &= ~FSCR_SCV; |
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cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV; |
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} |
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/* |
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* Tell the hypervisor that we want our exceptions to |
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* be taken in little endian mode. |
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* |
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* We don't call this for big endian as our calling convention |
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* makes us always enter in BE, and the call may fail under |
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* some circumstances with kdump. |
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*/ |
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#ifdef __LITTLE_ENDIAN__ |
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pseries_little_endian_exceptions(); |
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#endif |
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} else { |
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/* Set endian mode using OPAL */ |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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opal_configure_cores(); |
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/* AIL on native is done in cpu_ready_for_interrupts() */ |
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} |
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} |
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static void cpu_ready_for_interrupts(void) |
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{ |
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/* |
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* Enable AIL if supported, and we are in hypervisor mode. This |
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* is called once for every processor. |
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* |
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* If we are not in hypervisor mode the job is done once for |
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* the whole partition in configure_exceptions(). |
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*/ |
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if (cpu_has_feature(CPU_FTR_HVMODE)) { |
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unsigned long lpcr = mfspr(SPRN_LPCR); |
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unsigned long new_lpcr = lpcr; |
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if (cpu_has_feature(CPU_FTR_ARCH_31)) { |
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/* P10 DD1 does not have HAIL */ |
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if (pvr_version_is(PVR_POWER10) && |
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(mfspr(SPRN_PVR) & 0xf00) == 0x100) |
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new_lpcr |= LPCR_AIL_3; |
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else |
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new_lpcr |= LPCR_HAIL; |
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} else if (cpu_has_feature(CPU_FTR_ARCH_207S)) { |
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new_lpcr |= LPCR_AIL_3; |
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} |
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if (new_lpcr != lpcr) |
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mtspr(SPRN_LPCR, new_lpcr); |
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} |
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/* |
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* Set HFSCR:TM based on CPU features: |
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* In the special case of TM no suspend (P9N DD2.1), Linux is |
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* told TM is off via the dt-ftrs but told to (partially) use |
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* it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM] |
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* will be off from dt-ftrs but we need to turn it on for the |
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* no suspend case. |
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*/ |
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if (cpu_has_feature(CPU_FTR_HVMODE)) { |
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if (cpu_has_feature(CPU_FTR_TM_COMP)) |
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mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM); |
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else |
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mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM); |
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} |
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/* Set IR and DR in PACA MSR */ |
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get_paca()->kernel_msr = MSR_KERNEL; |
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} |
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unsigned long spr_default_dscr = 0; |
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static void __init record_spr_defaults(void) |
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{ |
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if (early_cpu_has_feature(CPU_FTR_DSCR)) |
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spr_default_dscr = mfspr(SPRN_DSCR); |
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} |
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/* |
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* Early initialization entry point. This is called by head.S |
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* with MMU translation disabled. We rely on the "feature" of |
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* the CPU that ignores the top 2 bits of the address in real |
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* mode so we can access kernel globals normally provided we |
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* only toy with things in the RMO region. From here, we do |
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* some early parsing of the device-tree to setup out MEMBLOCK |
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* data structures, and allocate & initialize the hash table |
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* and segment tables so we can start running with translation |
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* enabled. |
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* |
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* It is this function which will call the probe() callback of |
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* the various platform types and copy the matching one to the |
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* global ppc_md structure. Your platform can eventually do |
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* some very early initializations from the probe() routine, but |
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* this is not recommended, be very careful as, for example, the |
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* device-tree is not accessible via normal means at this point. |
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*/ |
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void __init early_setup(unsigned long dt_ptr) |
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{ |
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static __initdata struct paca_struct boot_paca; |
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/* -------- printk is _NOT_ safe to use here ! ------- */ |
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/* |
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* Assume we're on cpu 0 for now. |
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* |
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* We need to load a PACA very early for a few reasons. |
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* |
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* The stack protector canary is stored in the paca, so as soon as we |
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* call any stack protected code we need r13 pointing somewhere valid. |
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* |
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* If we are using kcov it will call in_task() in its instrumentation, |
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* which relies on the current task from the PACA. |
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* |
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* dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as |
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* printk(), which can trigger both stack protector and kcov. |
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* |
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* percpu variables and spin locks also use the paca. |
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* |
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* So set up a temporary paca. It will be replaced below once we know |
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* what CPU we are on. |
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*/ |
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initialise_paca(&boot_paca, 0); |
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setup_paca(&boot_paca); |
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fixup_boot_paca(); |
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/* -------- printk is now safe to use ------- */ |
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/* Try new device tree based feature discovery ... */ |
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if (!dt_cpu_ftrs_init(__va(dt_ptr))) |
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/* Otherwise use the old style CPU table */ |
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identify_cpu(0, mfspr(SPRN_PVR)); |
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/* Enable early debugging if any specified (see udbg.h) */ |
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udbg_early_init(); |
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udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr); |
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/* |
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* Do early initialization using the flattened device |
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* tree, such as retrieving the physical memory map or |
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* calculating/retrieving the hash table size. |
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*/ |
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early_init_devtree(__va(dt_ptr)); |
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/* Now we know the logical id of our boot cpu, setup the paca. */ |
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if (boot_cpuid != 0) { |
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/* Poison paca_ptrs[0] again if it's not the boot cpu */ |
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memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0])); |
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} |
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setup_paca(paca_ptrs[boot_cpuid]); |
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fixup_boot_paca(); |
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/* |
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* Configure exception handlers. This include setting up trampolines |
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* if needed, setting exception endian mode, etc... |
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*/ |
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configure_exceptions(); |
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/* |
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* Configure Kernel Userspace Protection. This needs to happen before |
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* feature fixups for platforms that implement this using features. |
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*/ |
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setup_kup(); |
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/* Apply all the dynamic patching */ |
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apply_feature_fixups(); |
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setup_feature_keys(); |
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/* Initialize the hash table or TLB handling */ |
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early_init_mmu(); |
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early_ioremap_setup(); |
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|
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/* |
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* After firmware and early platform setup code has set things up, |
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* we note the SPR values for configurable control/performance |
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* registers, and use those as initial defaults. |
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*/ |
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record_spr_defaults(); |
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/* |
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* At this point, we can let interrupts switch to virtual mode |
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* (the MMU has been setup), so adjust the MSR in the PACA to |
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* have IR and DR set and enable AIL if it exists |
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*/ |
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cpu_ready_for_interrupts(); |
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|
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/* |
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* We enable ftrace here, but since we only support DYNAMIC_FTRACE, it |
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* will only actually get enabled on the boot cpu much later once |
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* ftrace itself has been initialized. |
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*/ |
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this_cpu_enable_ftrace(); |
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udbg_printf(" <- %s()\n", __func__); |
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#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX |
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/* |
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* This needs to be done *last* (after the above udbg_printf() even) |
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* |
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* Right after we return from this function, we turn on the MMU |
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* which means the real-mode access trick that btext does will |
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* no longer work, it needs to switch to using a real MMU |
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* mapping. This call will ensure that it does |
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*/ |
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btext_map(); |
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#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ |
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} |
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#ifdef CONFIG_SMP |
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void early_setup_secondary(void) |
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{ |
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/* Mark interrupts disabled in PACA */ |
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irq_soft_mask_set(IRQS_DISABLED); |
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|
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/* Initialize the hash table or TLB handling */ |
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early_init_mmu_secondary(); |
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/* Perform any KUP setup that is per-cpu */ |
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setup_kup(); |
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/* |
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* At this point, we can let interrupts switch to virtual mode |
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* (the MMU has been setup), so adjust the MSR in the PACA to |
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* have IR and DR set. |
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*/ |
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cpu_ready_for_interrupts(); |
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} |
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#endif /* CONFIG_SMP */ |
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void panic_smp_self_stop(void) |
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{ |
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hard_irq_disable(); |
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spin_begin(); |
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while (1) |
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spin_cpu_relax(); |
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} |
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) |
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static bool use_spinloop(void) |
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{ |
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if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { |
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/* |
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* See comments in head_64.S -- not all platforms insert |
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* secondaries at __secondary_hold and wait at the spin |
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* loop. |
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*/ |
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if (firmware_has_feature(FW_FEATURE_OPAL)) |
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return false; |
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return true; |
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} |
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|
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/* |
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* When book3e boots from kexec, the ePAPR spin table does |
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* not get used. |
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*/ |
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return of_property_read_bool(of_chosen, "linux,booted-from-kexec"); |
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} |
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void smp_release_cpus(void) |
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{ |
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unsigned long *ptr; |
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int i; |
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|
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if (!use_spinloop()) |
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return; |
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|
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/* All secondary cpus are spinning on a common spinloop, release them |
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* all now so they can start to spin on their individual paca |
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* spinloops. For non SMP kernels, the secondary cpus never get out |
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* of the common spinloop. |
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*/ |
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|
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ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop |
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- PHYSICAL_START); |
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*ptr = ppc_function_entry(generic_secondary_smp_init); |
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|
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/* And wait a bit for them to catch up */ |
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for (i = 0; i < 100000; i++) { |
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mb(); |
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HMT_low(); |
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if (spinning_secondaries == 0) |
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break; |
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udelay(1); |
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} |
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pr_debug("spinning_secondaries = %d\n", spinning_secondaries); |
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} |
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#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */ |
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|
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/* |
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* Initialize some remaining members of the ppc64_caches and systemcfg |
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* structures |
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* (at least until we get rid of them completely). This is mostly some |
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* cache informations about the CPU that will be used by cache flush |
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* routines and/or provided to userland |
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*/ |
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|
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static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize, |
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u32 bsize, u32 sets) |
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{ |
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info->size = size; |
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info->sets = sets; |
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info->line_size = lsize; |
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info->block_size = bsize; |
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info->log_block_size = __ilog2(bsize); |
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if (bsize) |
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info->blocks_per_page = PAGE_SIZE / bsize; |
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else |
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info->blocks_per_page = 0; |
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|
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if (sets == 0) |
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info->assoc = 0xffff; |
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else |
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info->assoc = size / (sets * lsize); |
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} |
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|
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static bool __init parse_cache_info(struct device_node *np, |
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bool icache, |
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struct ppc_cache_info *info) |
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{ |
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static const char *ipropnames[] __initdata = { |
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"i-cache-size", |
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"i-cache-sets", |
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"i-cache-block-size", |
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"i-cache-line-size", |
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}; |
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static const char *dpropnames[] __initdata = { |
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"d-cache-size", |
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"d-cache-sets", |
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"d-cache-block-size", |
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"d-cache-line-size", |
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}; |
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const char **propnames = icache ? ipropnames : dpropnames; |
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const __be32 *sizep, *lsizep, *bsizep, *setsp; |
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u32 size, lsize, bsize, sets; |
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bool success = true; |
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|
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size = 0; |
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sets = -1u; |
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lsize = bsize = cur_cpu_spec->dcache_bsize; |
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sizep = of_get_property(np, propnames[0], NULL); |
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if (sizep != NULL) |
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size = be32_to_cpu(*sizep); |
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setsp = of_get_property(np, propnames[1], NULL); |
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if (setsp != NULL) |
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sets = be32_to_cpu(*setsp); |
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bsizep = of_get_property(np, propnames[2], NULL); |
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lsizep = of_get_property(np, propnames[3], NULL); |
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if (bsizep == NULL) |
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bsizep = lsizep; |
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if (lsizep == NULL) |
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lsizep = bsizep; |
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if (lsizep != NULL) |
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lsize = be32_to_cpu(*lsizep); |
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if (bsizep != NULL) |
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bsize = be32_to_cpu(*bsizep); |
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if (sizep == NULL || bsizep == NULL || lsizep == NULL) |
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success = false; |
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|
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/* |
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* OF is weird .. it represents fully associative caches |
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* as "1 way" which doesn't make much sense and doesn't |
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* leave room for direct mapped. We'll assume that 0 |
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* in OF means direct mapped for that reason. |
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*/ |
|
if (sets == 1) |
|
sets = 0; |
|
else if (sets == 0) |
|
sets = 1; |
|
|
|
init_cache_info(info, size, lsize, bsize, sets); |
|
|
|
return success; |
|
} |
|
|
|
void __init initialize_cache_info(void) |
|
{ |
|
struct device_node *cpu = NULL, *l2, *l3 = NULL; |
|
u32 pvr; |
|
|
|
/* |
|
* All shipping POWER8 machines have a firmware bug that |
|
* puts incorrect information in the device-tree. This will |
|
* be (hopefully) fixed for future chips but for now hard |
|
* code the values if we are running on one of these |
|
*/ |
|
pvr = PVR_VER(mfspr(SPRN_PVR)); |
|
if (pvr == PVR_POWER8 || pvr == PVR_POWER8E || |
|
pvr == PVR_POWER8NVL) { |
|
/* size lsize blk sets */ |
|
init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32); |
|
init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64); |
|
init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512); |
|
init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192); |
|
} else |
|
cpu = of_find_node_by_type(NULL, "cpu"); |
|
|
|
/* |
|
* We're assuming *all* of the CPUs have the same |
|
* d-cache and i-cache sizes... -Peter |
|
*/ |
|
if (cpu) { |
|
if (!parse_cache_info(cpu, false, &ppc64_caches.l1d)) |
|
pr_warn("Argh, can't find dcache properties !\n"); |
|
|
|
if (!parse_cache_info(cpu, true, &ppc64_caches.l1i)) |
|
pr_warn("Argh, can't find icache properties !\n"); |
|
|
|
/* |
|
* Try to find the L2 and L3 if any. Assume they are |
|
* unified and use the D-side properties. |
|
*/ |
|
l2 = of_find_next_cache_node(cpu); |
|
of_node_put(cpu); |
|
if (l2) { |
|
parse_cache_info(l2, false, &ppc64_caches.l2); |
|
l3 = of_find_next_cache_node(l2); |
|
of_node_put(l2); |
|
} |
|
if (l3) { |
|
parse_cache_info(l3, false, &ppc64_caches.l3); |
|
of_node_put(l3); |
|
} |
|
} |
|
|
|
/* For use by binfmt_elf */ |
|
dcache_bsize = ppc64_caches.l1d.block_size; |
|
icache_bsize = ppc64_caches.l1i.block_size; |
|
|
|
cur_cpu_spec->dcache_bsize = dcache_bsize; |
|
cur_cpu_spec->icache_bsize = icache_bsize; |
|
} |
|
|
|
/* |
|
* This returns the limit below which memory accesses to the linear |
|
* mapping are guarnateed not to cause an architectural exception (e.g., |
|
* TLB or SLB miss fault). |
|
* |
|
* This is used to allocate PACAs and various interrupt stacks that |
|
* that are accessed early in interrupt handlers that must not cause |
|
* re-entrant interrupts. |
|
*/ |
|
__init u64 ppc64_bolted_size(void) |
|
{ |
|
#ifdef CONFIG_PPC_BOOK3E |
|
/* Freescale BookE bolts the entire linear mapping */ |
|
/* XXX: BookE ppc64_rma_limit setup seems to disagree? */ |
|
if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) |
|
return linear_map_top; |
|
/* Other BookE, we assume the first GB is bolted */ |
|
return 1ul << 30; |
|
#else |
|
/* BookS radix, does not take faults on linear mapping */ |
|
if (early_radix_enabled()) |
|
return ULONG_MAX; |
|
|
|
/* BookS hash, the first segment is bolted */ |
|
if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
|
return 1UL << SID_SHIFT_1T; |
|
return 1UL << SID_SHIFT; |
|
#endif |
|
} |
|
|
|
static void *__init alloc_stack(unsigned long limit, int cpu) |
|
{ |
|
void *ptr; |
|
|
|
BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16); |
|
|
|
ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN, |
|
MEMBLOCK_LOW_LIMIT, limit, |
|
early_cpu_to_node(cpu)); |
|
if (!ptr) |
|
panic("cannot allocate stacks"); |
|
|
|
return ptr; |
|
} |
|
|
|
void __init irqstack_early_init(void) |
|
{ |
|
u64 limit = ppc64_bolted_size(); |
|
unsigned int i; |
|
|
|
/* |
|
* Interrupt stacks must be in the first segment since we |
|
* cannot afford to take SLB misses on them. They are not |
|
* accessed in realmode. |
|
*/ |
|
for_each_possible_cpu(i) { |
|
softirq_ctx[i] = alloc_stack(limit, i); |
|
hardirq_ctx[i] = alloc_stack(limit, i); |
|
} |
|
} |
|
|
|
#ifdef CONFIG_PPC_BOOK3E |
|
void __init exc_lvl_early_init(void) |
|
{ |
|
unsigned int i; |
|
|
|
for_each_possible_cpu(i) { |
|
void *sp; |
|
|
|
sp = alloc_stack(ULONG_MAX, i); |
|
critirq_ctx[i] = sp; |
|
paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE; |
|
|
|
sp = alloc_stack(ULONG_MAX, i); |
|
dbgirq_ctx[i] = sp; |
|
paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE; |
|
|
|
sp = alloc_stack(ULONG_MAX, i); |
|
mcheckirq_ctx[i] = sp; |
|
paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE; |
|
} |
|
|
|
if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC)) |
|
patch_exception(0x040, exc_debug_debug_book3e); |
|
} |
|
#endif |
|
|
|
/* |
|
* Stack space used when we detect a bad kernel stack pointer, and |
|
* early in SMP boots before relocation is enabled. Exclusive emergency |
|
* stack for machine checks. |
|
*/ |
|
void __init emergency_stack_init(void) |
|
{ |
|
u64 limit, mce_limit; |
|
unsigned int i; |
|
|
|
/* |
|
* Emergency stacks must be under 256MB, we cannot afford to take |
|
* SLB misses on them. The ABI also requires them to be 128-byte |
|
* aligned. |
|
* |
|
* Since we use these as temporary stacks during secondary CPU |
|
* bringup, machine check, system reset, and HMI, we need to get |
|
* at them in real mode. This means they must also be within the RMO |
|
* region. |
|
* |
|
* The IRQ stacks allocated elsewhere in this file are zeroed and |
|
* initialized in kernel/irq.c. These are initialized here in order |
|
* to have emergency stacks available as early as possible. |
|
*/ |
|
limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size); |
|
|
|
/* |
|
* Machine check on pseries calls rtas, but can't use the static |
|
* rtas_args due to a machine check hitting while the lock is held. |
|
* rtas args have to be under 4GB, so the machine check stack is |
|
* limited to 4GB so args can be put on stack. |
|
*/ |
|
if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G) |
|
mce_limit = SZ_4G; |
|
|
|
for_each_possible_cpu(i) { |
|
paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; |
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64 |
|
/* emergency stack for NMI exception handling. */ |
|
paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE; |
|
|
|
/* emergency stack for machine check exception handling. */ |
|
paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE; |
|
#endif |
|
} |
|
} |
|
|
|
#ifdef CONFIG_SMP |
|
/** |
|
* pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu |
|
* @cpu: cpu to allocate for |
|
* @size: size allocation in bytes |
|
* @align: alignment |
|
* |
|
* Allocate @size bytes aligned at @align for cpu @cpu. This wrapper |
|
* does the right thing for NUMA regardless of the current |
|
* configuration. |
|
* |
|
* RETURNS: |
|
* Pointer to the allocated area on success, NULL on failure. |
|
*/ |
|
static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size, |
|
size_t align) |
|
{ |
|
const unsigned long goal = __pa(MAX_DMA_ADDRESS); |
|
#ifdef CONFIG_NEED_MULTIPLE_NODES |
|
int node = early_cpu_to_node(cpu); |
|
void *ptr; |
|
|
|
if (!node_online(node) || !NODE_DATA(node)) { |
|
ptr = memblock_alloc_from(size, align, goal); |
|
pr_info("cpu %d has no node %d or node-local memory\n", |
|
cpu, node); |
|
pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n", |
|
cpu, size, __pa(ptr)); |
|
} else { |
|
ptr = memblock_alloc_try_nid(size, align, goal, |
|
MEMBLOCK_ALLOC_ACCESSIBLE, node); |
|
pr_debug("per cpu data for cpu%d %lu bytes on node%d at " |
|
"%016lx\n", cpu, size, node, __pa(ptr)); |
|
} |
|
return ptr; |
|
#else |
|
return memblock_alloc_from(size, align, goal); |
|
#endif |
|
} |
|
|
|
static void __init pcpu_free_bootmem(void *ptr, size_t size) |
|
{ |
|
memblock_free(__pa(ptr), size); |
|
} |
|
|
|
static int pcpu_cpu_distance(unsigned int from, unsigned int to) |
|
{ |
|
if (early_cpu_to_node(from) == early_cpu_to_node(to)) |
|
return LOCAL_DISTANCE; |
|
else |
|
return REMOTE_DISTANCE; |
|
} |
|
|
|
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly; |
|
EXPORT_SYMBOL(__per_cpu_offset); |
|
|
|
static void __init pcpu_populate_pte(unsigned long addr) |
|
{ |
|
pgd_t *pgd = pgd_offset_k(addr); |
|
p4d_t *p4d; |
|
pud_t *pud; |
|
pmd_t *pmd; |
|
|
|
p4d = p4d_offset(pgd, addr); |
|
if (p4d_none(*p4d)) { |
|
pud_t *new; |
|
|
|
new = memblock_alloc(PUD_TABLE_SIZE, PUD_TABLE_SIZE); |
|
if (!new) |
|
goto err_alloc; |
|
p4d_populate(&init_mm, p4d, new); |
|
} |
|
|
|
pud = pud_offset(p4d, addr); |
|
if (pud_none(*pud)) { |
|
pmd_t *new; |
|
|
|
new = memblock_alloc(PMD_TABLE_SIZE, PMD_TABLE_SIZE); |
|
if (!new) |
|
goto err_alloc; |
|
pud_populate(&init_mm, pud, new); |
|
} |
|
|
|
pmd = pmd_offset(pud, addr); |
|
if (!pmd_present(*pmd)) { |
|
pte_t *new; |
|
|
|
new = memblock_alloc(PTE_TABLE_SIZE, PTE_TABLE_SIZE); |
|
if (!new) |
|
goto err_alloc; |
|
pmd_populate_kernel(&init_mm, pmd, new); |
|
} |
|
|
|
return; |
|
|
|
err_alloc: |
|
panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n", |
|
__func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); |
|
} |
|
|
|
|
|
void __init setup_per_cpu_areas(void) |
|
{ |
|
const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE; |
|
size_t atom_size; |
|
unsigned long delta; |
|
unsigned int cpu; |
|
int rc = -EINVAL; |
|
|
|
/* |
|
* Linear mapping is one of 4K, 1M and 16M. For 4K, no need |
|
* to group units. For larger mappings, use 1M atom which |
|
* should be large enough to contain a number of units. |
|
*/ |
|
if (mmu_linear_psize == MMU_PAGE_4K) |
|
atom_size = PAGE_SIZE; |
|
else |
|
atom_size = 1 << 20; |
|
|
|
if (pcpu_chosen_fc != PCPU_FC_PAGE) { |
|
rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance, |
|
pcpu_alloc_bootmem, pcpu_free_bootmem); |
|
if (rc) |
|
pr_warn("PERCPU: %s allocator failed (%d), " |
|
"falling back to page size\n", |
|
pcpu_fc_names[pcpu_chosen_fc], rc); |
|
} |
|
|
|
if (rc < 0) |
|
rc = pcpu_page_first_chunk(0, pcpu_alloc_bootmem, pcpu_free_bootmem, |
|
pcpu_populate_pte); |
|
if (rc < 0) |
|
panic("cannot initialize percpu area (err=%d)", rc); |
|
|
|
delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
|
for_each_possible_cpu(cpu) { |
|
__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu]; |
|
paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu]; |
|
} |
|
} |
|
#endif |
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE |
|
unsigned long memory_block_size_bytes(void) |
|
{ |
|
if (ppc_md.memory_block_size) |
|
return ppc_md.memory_block_size(); |
|
|
|
return MIN_MEMORY_BLOCK_SIZE; |
|
} |
|
#endif |
|
|
|
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) |
|
struct ppc_pci_io ppc_pci_io; |
|
EXPORT_SYMBOL(ppc_pci_io); |
|
#endif |
|
|
|
#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF |
|
u64 hw_nmi_get_sample_period(int watchdog_thresh) |
|
{ |
|
return ppc_proc_freq * watchdog_thresh; |
|
} |
|
#endif |
|
|
|
/* |
|
* The perf based hardlockup detector breaks PMU event based branches, so |
|
* disable it by default. Book3S has a soft-nmi hardlockup detector based |
|
* on the decrementer interrupt, so it does not suffer from this problem. |
|
* |
|
* It is likely to get false positives in VM guests, so disable it there |
|
* by default too. |
|
*/ |
|
static int __init disable_hardlockup_detector(void) |
|
{ |
|
#ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF |
|
hardlockup_detector_disable(); |
|
#else |
|
if (firmware_has_feature(FW_FEATURE_LPAR)) |
|
hardlockup_detector_disable(); |
|
#endif |
|
|
|
return 0; |
|
} |
|
early_initcall(disable_hardlockup_detector); |
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64 |
|
static enum l1d_flush_type enabled_flush_types; |
|
static void *l1d_flush_fallback_area; |
|
static bool no_rfi_flush; |
|
static bool no_entry_flush; |
|
static bool no_uaccess_flush; |
|
bool rfi_flush; |
|
bool entry_flush; |
|
bool uaccess_flush; |
|
DEFINE_STATIC_KEY_FALSE(uaccess_flush_key); |
|
EXPORT_SYMBOL(uaccess_flush_key); |
|
|
|
static int __init handle_no_rfi_flush(char *p) |
|
{ |
|
pr_info("rfi-flush: disabled on command line."); |
|
no_rfi_flush = true; |
|
return 0; |
|
} |
|
early_param("no_rfi_flush", handle_no_rfi_flush); |
|
|
|
static int __init handle_no_entry_flush(char *p) |
|
{ |
|
pr_info("entry-flush: disabled on command line."); |
|
no_entry_flush = true; |
|
return 0; |
|
} |
|
early_param("no_entry_flush", handle_no_entry_flush); |
|
|
|
static int __init handle_no_uaccess_flush(char *p) |
|
{ |
|
pr_info("uaccess-flush: disabled on command line."); |
|
no_uaccess_flush = true; |
|
return 0; |
|
} |
|
early_param("no_uaccess_flush", handle_no_uaccess_flush); |
|
|
|
/* |
|
* The RFI flush is not KPTI, but because users will see doco that says to use |
|
* nopti we hijack that option here to also disable the RFI flush. |
|
*/ |
|
static int __init handle_no_pti(char *p) |
|
{ |
|
pr_info("rfi-flush: disabling due to 'nopti' on command line.\n"); |
|
handle_no_rfi_flush(NULL); |
|
return 0; |
|
} |
|
early_param("nopti", handle_no_pti); |
|
|
|
static void do_nothing(void *unused) |
|
{ |
|
/* |
|
* We don't need to do the flush explicitly, just enter+exit kernel is |
|
* sufficient, the RFI exit handlers will do the right thing. |
|
*/ |
|
} |
|
|
|
void rfi_flush_enable(bool enable) |
|
{ |
|
if (enable) { |
|
do_rfi_flush_fixups(enabled_flush_types); |
|
on_each_cpu(do_nothing, NULL, 1); |
|
} else |
|
do_rfi_flush_fixups(L1D_FLUSH_NONE); |
|
|
|
rfi_flush = enable; |
|
} |
|
|
|
static void entry_flush_enable(bool enable) |
|
{ |
|
if (enable) { |
|
do_entry_flush_fixups(enabled_flush_types); |
|
on_each_cpu(do_nothing, NULL, 1); |
|
} else { |
|
do_entry_flush_fixups(L1D_FLUSH_NONE); |
|
} |
|
|
|
entry_flush = enable; |
|
} |
|
|
|
static void uaccess_flush_enable(bool enable) |
|
{ |
|
if (enable) { |
|
do_uaccess_flush_fixups(enabled_flush_types); |
|
static_branch_enable(&uaccess_flush_key); |
|
on_each_cpu(do_nothing, NULL, 1); |
|
} else { |
|
static_branch_disable(&uaccess_flush_key); |
|
do_uaccess_flush_fixups(L1D_FLUSH_NONE); |
|
} |
|
|
|
uaccess_flush = enable; |
|
} |
|
|
|
static void __ref init_fallback_flush(void) |
|
{ |
|
u64 l1d_size, limit; |
|
int cpu; |
|
|
|
/* Only allocate the fallback flush area once (at boot time). */ |
|
if (l1d_flush_fallback_area) |
|
return; |
|
|
|
l1d_size = ppc64_caches.l1d.size; |
|
|
|
/* |
|
* If there is no d-cache-size property in the device tree, l1d_size |
|
* could be zero. That leads to the loop in the asm wrapping around to |
|
* 2^64-1, and then walking off the end of the fallback area and |
|
* eventually causing a page fault which is fatal. Just default to |
|
* something vaguely sane. |
|
*/ |
|
if (!l1d_size) |
|
l1d_size = (64 * 1024); |
|
|
|
limit = min(ppc64_bolted_size(), ppc64_rma_size); |
|
|
|
/* |
|
* Align to L1d size, and size it at 2x L1d size, to catch possible |
|
* hardware prefetch runoff. We don't have a recipe for load patterns to |
|
* reliably avoid the prefetcher. |
|
*/ |
|
l1d_flush_fallback_area = memblock_alloc_try_nid(l1d_size * 2, |
|
l1d_size, MEMBLOCK_LOW_LIMIT, |
|
limit, NUMA_NO_NODE); |
|
if (!l1d_flush_fallback_area) |
|
panic("%s: Failed to allocate %llu bytes align=0x%llx max_addr=%pa\n", |
|
__func__, l1d_size * 2, l1d_size, &limit); |
|
|
|
|
|
for_each_possible_cpu(cpu) { |
|
struct paca_struct *paca = paca_ptrs[cpu]; |
|
paca->rfi_flush_fallback_area = l1d_flush_fallback_area; |
|
paca->l1d_flush_size = l1d_size; |
|
} |
|
} |
|
|
|
void setup_rfi_flush(enum l1d_flush_type types, bool enable) |
|
{ |
|
if (types & L1D_FLUSH_FALLBACK) { |
|
pr_info("rfi-flush: fallback displacement flush available\n"); |
|
init_fallback_flush(); |
|
} |
|
|
|
if (types & L1D_FLUSH_ORI) |
|
pr_info("rfi-flush: ori type flush available\n"); |
|
|
|
if (types & L1D_FLUSH_MTTRIG) |
|
pr_info("rfi-flush: mttrig type flush available\n"); |
|
|
|
enabled_flush_types = types; |
|
|
|
if (!cpu_mitigations_off() && !no_rfi_flush) |
|
rfi_flush_enable(enable); |
|
} |
|
|
|
void setup_entry_flush(bool enable) |
|
{ |
|
if (cpu_mitigations_off()) |
|
return; |
|
|
|
if (!no_entry_flush) |
|
entry_flush_enable(enable); |
|
} |
|
|
|
void setup_uaccess_flush(bool enable) |
|
{ |
|
if (cpu_mitigations_off()) |
|
return; |
|
|
|
if (!no_uaccess_flush) |
|
uaccess_flush_enable(enable); |
|
} |
|
|
|
#ifdef CONFIG_DEBUG_FS |
|
static int rfi_flush_set(void *data, u64 val) |
|
{ |
|
bool enable; |
|
|
|
if (val == 1) |
|
enable = true; |
|
else if (val == 0) |
|
enable = false; |
|
else |
|
return -EINVAL; |
|
|
|
/* Only do anything if we're changing state */ |
|
if (enable != rfi_flush) |
|
rfi_flush_enable(enable); |
|
|
|
return 0; |
|
} |
|
|
|
static int rfi_flush_get(void *data, u64 *val) |
|
{ |
|
*val = rfi_flush ? 1 : 0; |
|
return 0; |
|
} |
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n"); |
|
|
|
static int entry_flush_set(void *data, u64 val) |
|
{ |
|
bool enable; |
|
|
|
if (val == 1) |
|
enable = true; |
|
else if (val == 0) |
|
enable = false; |
|
else |
|
return -EINVAL; |
|
|
|
/* Only do anything if we're changing state */ |
|
if (enable != entry_flush) |
|
entry_flush_enable(enable); |
|
|
|
return 0; |
|
} |
|
|
|
static int entry_flush_get(void *data, u64 *val) |
|
{ |
|
*val = entry_flush ? 1 : 0; |
|
return 0; |
|
} |
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(fops_entry_flush, entry_flush_get, entry_flush_set, "%llu\n"); |
|
|
|
static int uaccess_flush_set(void *data, u64 val) |
|
{ |
|
bool enable; |
|
|
|
if (val == 1) |
|
enable = true; |
|
else if (val == 0) |
|
enable = false; |
|
else |
|
return -EINVAL; |
|
|
|
/* Only do anything if we're changing state */ |
|
if (enable != uaccess_flush) |
|
uaccess_flush_enable(enable); |
|
|
|
return 0; |
|
} |
|
|
|
static int uaccess_flush_get(void *data, u64 *val) |
|
{ |
|
*val = uaccess_flush ? 1 : 0; |
|
return 0; |
|
} |
|
|
|
DEFINE_SIMPLE_ATTRIBUTE(fops_uaccess_flush, uaccess_flush_get, uaccess_flush_set, "%llu\n"); |
|
|
|
static __init int rfi_flush_debugfs_init(void) |
|
{ |
|
debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush); |
|
debugfs_create_file("entry_flush", 0600, powerpc_debugfs_root, NULL, &fops_entry_flush); |
|
debugfs_create_file("uaccess_flush", 0600, powerpc_debugfs_root, NULL, &fops_uaccess_flush); |
|
return 0; |
|
} |
|
device_initcall(rfi_flush_debugfs_init); |
|
#endif |
|
#endif /* CONFIG_PPC_BOOK3S_64 */
|
|
|