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225 lines
5.2 KiB
225 lines
5.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Common prep/pmac/chrp boot and setup code. |
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*/ |
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#include <linux/module.h> |
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#include <linux/string.h> |
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#include <linux/sched.h> |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/reboot.h> |
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#include <linux/delay.h> |
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#include <linux/initrd.h> |
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#include <linux/tty.h> |
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#include <linux/seq_file.h> |
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#include <linux/root_dev.h> |
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#include <linux/cpu.h> |
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#include <linux/console.h> |
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#include <linux/memblock.h> |
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#include <linux/export.h> |
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#include <linux/nvram.h> |
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#include <linux/pgtable.h> |
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#include <asm/io.h> |
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#include <asm/prom.h> |
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#include <asm/processor.h> |
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#include <asm/setup.h> |
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#include <asm/smp.h> |
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#include <asm/elf.h> |
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#include <asm/cputable.h> |
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#include <asm/bootx.h> |
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#include <asm/btext.h> |
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#include <asm/machdep.h> |
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#include <linux/uaccess.h> |
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#include <asm/pmac_feature.h> |
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#include <asm/sections.h> |
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#include <asm/nvram.h> |
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#include <asm/xmon.h> |
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#include <asm/time.h> |
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#include <asm/serial.h> |
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#include <asm/udbg.h> |
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#include <asm/code-patching.h> |
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#include <asm/cpu_has_feature.h> |
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#include <asm/asm-prototypes.h> |
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#include <asm/kdump.h> |
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#include <asm/feature-fixups.h> |
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#include <asm/early_ioremap.h> |
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#include "setup.h" |
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#define DBG(fmt...) |
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extern void bootx_init(unsigned long r4, unsigned long phys); |
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int boot_cpuid_phys; |
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EXPORT_SYMBOL_GPL(boot_cpuid_phys); |
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int smp_hw_index[NR_CPUS]; |
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EXPORT_SYMBOL(smp_hw_index); |
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unsigned int DMA_MODE_READ; |
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unsigned int DMA_MODE_WRITE; |
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EXPORT_SYMBOL(DMA_MODE_READ); |
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EXPORT_SYMBOL(DMA_MODE_WRITE); |
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/* |
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* This is run before start_kernel(), the kernel has been relocated |
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* and we are running with enough of the MMU enabled to have our |
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* proper kernel virtual addresses |
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* |
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* We do the initial parsing of the flat device-tree and prepares |
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* for the MMU to be fully initialized. |
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*/ |
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notrace void __init machine_init(u64 dt_ptr) |
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{ |
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struct ppc_inst *addr = (struct ppc_inst *)patch_site_addr(&patch__memset_nocache); |
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struct ppc_inst insn; |
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/* Configure static keys first, now that we're relocated. */ |
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setup_feature_keys(); |
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early_ioremap_init(); |
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/* Enable early debugging if any specified (see udbg.h) */ |
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udbg_early_init(); |
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patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_INST_NOP)); |
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create_cond_branch(&insn, addr, branch_target(addr), 0x820000); |
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patch_instruction(addr, insn); /* replace b by bne cr0 */ |
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/* Do some early initialization based on the flat device tree */ |
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early_init_devtree(__va(dt_ptr)); |
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early_init_mmu(); |
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setup_kdump_trampoline(); |
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} |
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/* Checks "l2cr=xxxx" command-line option */ |
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static int __init ppc_setup_l2cr(char *str) |
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{ |
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if (cpu_has_feature(CPU_FTR_L2CR)) { |
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unsigned long val = simple_strtoul(str, NULL, 0); |
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printk(KERN_INFO "l2cr set to %lx\n", val); |
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_set_L2CR(0); /* force invalidate by disable cache */ |
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_set_L2CR(val); /* and enable it */ |
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} |
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return 1; |
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} |
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__setup("l2cr=", ppc_setup_l2cr); |
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/* Checks "l3cr=xxxx" command-line option */ |
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static int __init ppc_setup_l3cr(char *str) |
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{ |
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if (cpu_has_feature(CPU_FTR_L3CR)) { |
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unsigned long val = simple_strtoul(str, NULL, 0); |
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printk(KERN_INFO "l3cr set to %lx\n", val); |
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_set_L3CR(val); /* and enable it */ |
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} |
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return 1; |
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} |
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__setup("l3cr=", ppc_setup_l3cr); |
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static int __init ppc_init(void) |
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{ |
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/* clear the progress line */ |
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if (ppc_md.progress) |
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ppc_md.progress(" ", 0xffff); |
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/* call platform init */ |
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if (ppc_md.init != NULL) { |
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ppc_md.init(); |
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} |
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return 0; |
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} |
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arch_initcall(ppc_init); |
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static void *__init alloc_stack(void) |
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{ |
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void *ptr = memblock_alloc(THREAD_SIZE, THREAD_ALIGN); |
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if (!ptr) |
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panic("cannot allocate %d bytes for stack at %pS\n", |
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THREAD_SIZE, (void *)_RET_IP_); |
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return ptr; |
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} |
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void __init irqstack_early_init(void) |
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{ |
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unsigned int i; |
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if (IS_ENABLED(CONFIG_VMAP_STACK)) |
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return; |
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/* interrupt stacks must be in lowmem, we get that for free on ppc32 |
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* as the memblock is limited to lowmem by default */ |
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for_each_possible_cpu(i) { |
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softirq_ctx[i] = alloc_stack(); |
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hardirq_ctx[i] = alloc_stack(); |
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} |
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} |
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#ifdef CONFIG_VMAP_STACK |
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void *emergency_ctx[NR_CPUS] __ro_after_init = {[0] = &init_stack}; |
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void __init emergency_stack_init(void) |
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{ |
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unsigned int i; |
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for_each_possible_cpu(i) |
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emergency_ctx[i] = alloc_stack(); |
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} |
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#endif |
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
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void __init exc_lvl_early_init(void) |
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{ |
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unsigned int i, hw_cpu; |
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/* interrupt stacks must be in lowmem, we get that for free on ppc32 |
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* as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ |
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for_each_possible_cpu(i) { |
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#ifdef CONFIG_SMP |
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hw_cpu = get_hard_smp_processor_id(i); |
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#else |
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hw_cpu = 0; |
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#endif |
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critirq_ctx[hw_cpu] = alloc_stack(); |
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#ifdef CONFIG_BOOKE |
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dbgirq_ctx[hw_cpu] = alloc_stack(); |
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mcheckirq_ctx[hw_cpu] = alloc_stack(); |
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#endif |
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} |
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} |
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#endif |
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void __init setup_power_save(void) |
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{ |
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#ifdef CONFIG_PPC_BOOK3S_32 |
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if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
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cpu_has_feature(CPU_FTR_CAN_NAP)) |
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ppc_md.power_save = ppc6xx_idle; |
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#endif |
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#ifdef CONFIG_E500 |
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if (cpu_has_feature(CPU_FTR_CAN_DOZE) || |
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cpu_has_feature(CPU_FTR_CAN_NAP)) |
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ppc_md.power_save = e500_idle; |
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#endif |
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} |
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__init void initialize_cache_info(void) |
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{ |
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/* |
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* Set cache line size based on type of cpu as a default. |
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* Systems with OF can look in the properties on the cpu node(s) |
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* for a possibly more accurate value. |
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*/ |
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dcache_bsize = cur_cpu_spec->dcache_bsize; |
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icache_bsize = cur_cpu_spec->icache_bsize; |
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}
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