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517 lines
10 KiB
517 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* This file contains miscellaneous low-level functions. |
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
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* |
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu) |
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* and Paul Mackerras. |
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* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com) |
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* PPC64 updates by Dave Engebretsen (engebret@us.ibm.com) |
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*/ |
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#include <linux/sys.h> |
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#include <asm/unistd.h> |
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#include <asm/errno.h> |
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#include <asm/processor.h> |
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#include <asm/page.h> |
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#include <asm/cache.h> |
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#include <asm/ppc_asm.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/cputable.h> |
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#include <asm/thread_info.h> |
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#include <asm/kexec.h> |
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#include <asm/ptrace.h> |
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#include <asm/mmu.h> |
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#include <asm/export.h> |
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#include <asm/feature-fixups.h> |
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.text |
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_GLOBAL(call_do_softirq) |
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mflr r0 |
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std r0,16(r1) |
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stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) |
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mr r1,r3 |
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bl __do_softirq |
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ld r1,0(r1) |
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ld r0,16(r1) |
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mtlr r0 |
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blr |
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_GLOBAL(call_do_irq) |
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mflr r0 |
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std r0,16(r1) |
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stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4) |
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mr r1,r4 |
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bl __do_irq |
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ld r1,0(r1) |
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ld r0,16(r1) |
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mtlr r0 |
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blr |
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_GLOBAL(__bswapdi2) |
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EXPORT_SYMBOL(__bswapdi2) |
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srdi r8,r3,32 |
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rlwinm r7,r3,8,0xffffffff |
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rlwimi r7,r3,24,0,7 |
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rlwinm r9,r8,8,0xffffffff |
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rlwimi r7,r3,24,16,23 |
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rlwimi r9,r8,24,0,7 |
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rlwimi r9,r8,24,16,23 |
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sldi r7,r7,32 |
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or r3,r7,r9 |
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blr |
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#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX |
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_GLOBAL(rmci_on) |
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sync |
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isync |
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li r3,0x100 |
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rldicl r3,r3,32,0 |
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mfspr r5,SPRN_HID4 |
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or r5,r5,r3 |
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sync |
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mtspr SPRN_HID4,r5 |
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isync |
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slbia |
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isync |
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sync |
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blr |
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_GLOBAL(rmci_off) |
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sync |
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isync |
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li r3,0x100 |
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rldicl r3,r3,32,0 |
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mfspr r5,SPRN_HID4 |
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andc r5,r5,r3 |
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sync |
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mtspr SPRN_HID4,r5 |
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isync |
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slbia |
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isync |
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sync |
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blr |
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#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */ |
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#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) |
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/* |
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* Do an IO access in real mode |
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*/ |
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_GLOBAL(real_readb) |
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mfmsr r7 |
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ori r0,r7,MSR_DR |
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xori r0,r0,MSR_DR |
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sync |
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mtmsrd r0 |
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sync |
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isync |
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mfspr r6,SPRN_HID4 |
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rldicl r5,r6,32,0 |
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ori r5,r5,0x100 |
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rldicl r5,r5,32,0 |
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sync |
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mtspr SPRN_HID4,r5 |
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isync |
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slbia |
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isync |
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lbz r3,0(r3) |
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sync |
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mtspr SPRN_HID4,r6 |
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isync |
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slbia |
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isync |
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mtmsrd r7 |
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sync |
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isync |
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blr |
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/* |
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* Do an IO access in real mode |
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*/ |
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_GLOBAL(real_writeb) |
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mfmsr r7 |
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ori r0,r7,MSR_DR |
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xori r0,r0,MSR_DR |
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sync |
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mtmsrd r0 |
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sync |
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isync |
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mfspr r6,SPRN_HID4 |
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rldicl r5,r6,32,0 |
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ori r5,r5,0x100 |
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rldicl r5,r5,32,0 |
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sync |
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mtspr SPRN_HID4,r5 |
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isync |
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slbia |
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isync |
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stb r3,0(r4) |
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sync |
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mtspr SPRN_HID4,r6 |
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isync |
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slbia |
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isync |
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mtmsrd r7 |
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sync |
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isync |
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blr |
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#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */ |
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#ifdef CONFIG_PPC_PASEMI |
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_GLOBAL(real_205_readb) |
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mfmsr r7 |
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ori r0,r7,MSR_DR |
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xori r0,r0,MSR_DR |
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sync |
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mtmsrd r0 |
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sync |
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isync |
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LBZCIX(R3,R0,R3) |
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isync |
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mtmsrd r7 |
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sync |
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isync |
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blr |
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_GLOBAL(real_205_writeb) |
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mfmsr r7 |
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ori r0,r7,MSR_DR |
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xori r0,r0,MSR_DR |
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sync |
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mtmsrd r0 |
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sync |
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isync |
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STBCIX(R3,R0,R4) |
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isync |
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mtmsrd r7 |
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sync |
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isync |
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blr |
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#endif /* CONFIG_PPC_PASEMI */ |
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#if defined(CONFIG_CPU_FREQ_PMAC64) || defined(CONFIG_CPU_FREQ_MAPLE) |
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/* |
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* SCOM access functions for 970 (FX only for now) |
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* |
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* unsigned long scom970_read(unsigned int address); |
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* void scom970_write(unsigned int address, unsigned long value); |
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* |
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* The address passed in is the 24 bits register address. This code |
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* is 970 specific and will not check the status bits, so you should |
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* know what you are doing. |
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*/ |
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_GLOBAL(scom970_read) |
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/* interrupts off */ |
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mfmsr r4 |
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ori r0,r4,MSR_EE |
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xori r0,r0,MSR_EE |
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mtmsrd r0,1 |
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits |
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* (including parity). On current CPUs they must be 0'd, |
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* and finally or in RW bit |
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*/ |
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rlwinm r3,r3,8,0,15 |
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ori r3,r3,0x8000 |
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/* do the actual scom read */ |
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sync |
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mtspr SPRN_SCOMC,r3 |
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isync |
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mfspr r3,SPRN_SCOMD |
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isync |
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mfspr r0,SPRN_SCOMC |
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isync |
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/* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah |
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* that's the best we can do). Not implemented yet as we don't use |
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* the scom on any of the bogus CPUs yet, but may have to be done |
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* ultimately |
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*/ |
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/* restore interrupts */ |
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mtmsrd r4,1 |
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blr |
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_GLOBAL(scom970_write) |
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/* interrupts off */ |
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mfmsr r5 |
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ori r0,r5,MSR_EE |
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xori r0,r0,MSR_EE |
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mtmsrd r0,1 |
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/* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits |
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* (including parity). On current CPUs they must be 0'd. |
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*/ |
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rlwinm r3,r3,8,0,15 |
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sync |
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mtspr SPRN_SCOMD,r4 /* write data */ |
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isync |
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mtspr SPRN_SCOMC,r3 /* write command */ |
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isync |
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mfspr 3,SPRN_SCOMC |
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isync |
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/* restore interrupts */ |
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mtmsrd r5,1 |
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blr |
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#endif /* CONFIG_CPU_FREQ_PMAC64 || CONFIG_CPU_FREQ_MAPLE */ |
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/* kexec_wait(phys_cpu) |
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* |
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* wait for the flag to change, indicating this kernel is going away but |
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* the slave code for the next one is at addresses 0 to 100. |
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* |
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* This is used by all slaves, even those that did not find a matching |
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* paca in the secondary startup code. |
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* |
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* Physical (hardware) cpu id should be in r3. |
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*/ |
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_GLOBAL(kexec_wait) |
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bl 1f |
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1: mflr r5 |
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addi r5,r5,kexec_flag-1b |
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99: HMT_LOW |
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#ifdef CONFIG_KEXEC_CORE /* use no memory without kexec */ |
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lwz r4,0(r5) |
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cmpwi 0,r4,0 |
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beq 99b |
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#ifdef CONFIG_PPC_BOOK3S_64 |
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li r10,0x60 |
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mfmsr r11 |
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clrrdi r11,r11,1 /* Clear MSR_LE */ |
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mtsrr0 r10 |
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mtsrr1 r11 |
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rfid |
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#else |
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/* Create TLB entry in book3e_secondary_core_init */ |
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li r4,0 |
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ba 0x60 |
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#endif |
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#endif |
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/* this can be in text because we won't change it until we are |
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* running in real anyways |
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*/ |
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kexec_flag: |
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.long 0 |
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#ifdef CONFIG_KEXEC_CORE |
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#ifdef CONFIG_PPC_BOOK3E |
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/* |
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* BOOK3E has no real MMU mode, so we have to setup the initial TLB |
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* for a core to identity map v:0 to p:0. This current implementation |
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* assumes that 1G is enough for kexec. |
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*/ |
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kexec_create_tlb: |
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/* |
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* Invalidate all non-IPROT TLB entries to avoid any TLB conflict. |
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* IPROT TLB entries should be >= PAGE_OFFSET and thus not conflict. |
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*/ |
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PPC_TLBILX_ALL(0,R0) |
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sync |
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isync |
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mfspr r10,SPRN_TLB1CFG |
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andi. r10,r10,TLBnCFG_N_ENTRY /* Extract # entries */ |
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subi r10,r10,1 /* Last entry: no conflict with kernel text */ |
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lis r9,MAS0_TLBSEL(1)@h |
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rlwimi r9,r10,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r9) */ |
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/* Set up a temp identity mapping v:0 to p:0 and return to it. */ |
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mtspr SPRN_MAS0,r9 |
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lis r9,(MAS1_VALID|MAS1_IPROT)@h |
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ori r9,r9,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l |
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mtspr SPRN_MAS1,r9 |
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LOAD_REG_IMMEDIATE(r9, 0x0 | MAS2_M_IF_NEEDED) |
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mtspr SPRN_MAS2,r9 |
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LOAD_REG_IMMEDIATE(r9, 0x0 | MAS3_SR | MAS3_SW | MAS3_SX) |
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mtspr SPRN_MAS3,r9 |
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li r9,0 |
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mtspr SPRN_MAS7,r9 |
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tlbwe |
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isync |
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blr |
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#endif |
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/* kexec_smp_wait(void) |
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* |
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* call with interrupts off |
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* note: this is a terminal routine, it does not save lr |
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* |
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* get phys id from paca |
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* switch to real mode |
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* mark the paca as no longer used |
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* join other cpus in kexec_wait(phys_id) |
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*/ |
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_GLOBAL(kexec_smp_wait) |
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lhz r3,PACAHWCPUID(r13) |
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bl real_mode |
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li r4,KEXEC_STATE_REAL_MODE |
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stb r4,PACAKEXECSTATE(r13) |
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b kexec_wait |
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/* |
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* switch to real mode (turn mmu off) |
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* we use the early kernel trick that the hardware ignores bits |
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* 0 and 1 (big endian) of the effective address in real mode |
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* |
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* don't overwrite r3 here, it is live for kexec_wait above. |
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*/ |
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real_mode: /* assume normal blr return */ |
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#ifdef CONFIG_PPC_BOOK3E |
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/* Create an identity mapping. */ |
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b kexec_create_tlb |
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#else |
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1: li r9,MSR_RI |
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li r10,MSR_DR|MSR_IR |
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mflr r11 /* return address to SRR0 */ |
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mfmsr r12 |
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andc r9,r12,r9 |
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andc r10,r12,r10 |
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mtmsrd r9,1 |
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mtspr SPRN_SRR1,r10 |
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mtspr SPRN_SRR0,r11 |
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rfid |
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#endif |
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/* |
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* kexec_sequence(newstack, start, image, control, clear_all(), |
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copy_with_mmu_off) |
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* |
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* does the grungy work with stack switching and real mode switches |
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* also does simple calls to other code |
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*/ |
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_GLOBAL(kexec_sequence) |
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mflr r0 |
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std r0,16(r1) |
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/* switch stacks to newstack -- &kexec_stack.stack */ |
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stdu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3) |
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mr r1,r3 |
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li r0,0 |
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std r0,16(r1) |
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/* save regs for local vars on new stack. |
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* yes, we won't go back, but ... |
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*/ |
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std r31,-8(r1) |
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std r30,-16(r1) |
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std r29,-24(r1) |
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std r28,-32(r1) |
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std r27,-40(r1) |
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std r26,-48(r1) |
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std r25,-56(r1) |
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stdu r1,-STACK_FRAME_OVERHEAD-64(r1) |
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/* save args into preserved regs */ |
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mr r31,r3 /* newstack (both) */ |
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mr r30,r4 /* start (real) */ |
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mr r29,r5 /* image (virt) */ |
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mr r28,r6 /* control, unused */ |
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mr r27,r7 /* clear_all() fn desc */ |
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mr r26,r8 /* copy_with_mmu_off */ |
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lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */ |
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/* disable interrupts, we are overwriting kernel data next */ |
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#ifdef CONFIG_PPC_BOOK3E |
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wrteei 0 |
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#else |
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mfmsr r3 |
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rlwinm r3,r3,0,17,15 |
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mtmsrd r3,1 |
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#endif |
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/* We need to turn the MMU off unless we are in hash mode |
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* under a hypervisor |
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*/ |
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cmpdi r26,0 |
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beq 1f |
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bl real_mode |
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1: |
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/* copy dest pages, flush whole dest image */ |
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mr r3,r29 |
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bl kexec_copy_flush /* (image) */ |
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/* turn off mmu now if not done earlier */ |
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cmpdi r26,0 |
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bne 1f |
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bl real_mode |
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/* copy 0x100 bytes starting at start to 0 */ |
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1: li r3,0 |
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mr r4,r30 /* start, aka phys mem offset */ |
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li r5,0x100 |
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li r6,0 |
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bl copy_and_flush /* (dest, src, copy limit, start offset) */ |
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1: /* assume normal blr return */ |
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/* release other cpus to the new kernel secondary start at 0x60 */ |
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mflr r5 |
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li r6,1 |
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stw r6,kexec_flag-1b(5) |
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cmpdi r27,0 |
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beq 1f |
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/* clear out hardware hash page table and tlb */ |
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#ifdef PPC64_ELF_ABI_v1 |
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ld r12,0(r27) /* deref function descriptor */ |
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#else |
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mr r12,r27 |
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#endif |
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mtctr r12 |
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bctrl /* mmu_hash_ops.hpte_clear_all(void); */ |
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/* |
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* kexec image calling is: |
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* the first 0x100 bytes of the entry point are copied to 0 |
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* |
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* all slaves branch to slave = 0x60 (absolute) |
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* slave(phys_cpu_id); |
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* |
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* master goes to start = entry point |
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* start(phys_cpu_id, start, 0); |
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* |
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* |
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* a wrapper is needed to call existing kernels, here is an approximate |
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* description of one method: |
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* |
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* v2: (2.6.10) |
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* start will be near the boot_block (maybe 0x100 bytes before it?) |
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* it will have a 0x60, which will b to boot_block, where it will wait |
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* and 0 will store phys into struct boot-block and load r3 from there, |
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* copy kernel 0-0x100 and tell slaves to back down to 0x60 again |
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* |
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* v1: (2.6.9) |
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* boot block will have all cpus scanning device tree to see if they |
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* are the boot cpu ????? |
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* other device tree differences (prop sizes, va vs pa, etc)... |
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*/ |
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1: mr r3,r25 # my phys cpu |
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mr r4,r30 # start, aka phys mem offset |
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mtlr 4 |
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li r5,0 |
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blr /* image->start(physid, image->start, 0); */ |
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#endif /* CONFIG_KEXEC_CORE */
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