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53 lines
1.7 KiB
53 lines
1.7 KiB
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ |
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#ifndef _ASM_POWERPC_AUXVEC_H |
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#define _ASM_POWERPC_AUXVEC_H |
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/* |
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* We need to put in some extra aux table entries to tell glibc what |
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* the cache block size is, so it can use the dcbz instruction safely. |
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*/ |
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#define AT_DCACHEBSIZE 19 |
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#define AT_ICACHEBSIZE 20 |
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#define AT_UCACHEBSIZE 21 |
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/* A special ignored type value for PPC, for glibc compatibility. */ |
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#define AT_IGNOREPPC 22 |
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/* The vDSO location. We have to use the same value as x86 for glibc's |
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* sake :-) |
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*/ |
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#define AT_SYSINFO_EHDR 33 |
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/* |
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* AT_*CACHEBSIZE above represent the cache *block* size which is |
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* the size that is affected by the cache management instructions. |
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* |
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* It doesn't nececssarily matches the cache *line* size which is |
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* more of a performance tuning hint. Additionally the latter can |
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* be different for the different cache levels. |
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* |
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* The set of entries below represent more extensive information |
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* about the caches, in the form of two entry per cache type, |
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* one entry containing the cache size in bytes, and the other |
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* containing the cache line size in bytes in the bottom 16 bits |
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* and the cache associativity in the next 16 bits. |
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* |
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* The associativity is such that if N is the 16-bit value, the |
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* cache is N way set associative. A value if 0xffff means fully |
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* associative, a value of 1 means directly mapped. |
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* |
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* For all these fields, a value of 0 means that the information |
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* is not known. |
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*/ |
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#define AT_L1I_CACHESIZE 40 |
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#define AT_L1I_CACHEGEOMETRY 41 |
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#define AT_L1D_CACHESIZE 42 |
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#define AT_L1D_CACHEGEOMETRY 43 |
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#define AT_L2_CACHESIZE 44 |
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#define AT_L2_CACHEGEOMETRY 45 |
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#define AT_L3_CACHESIZE 46 |
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#define AT_L3_CACHEGEOMETRY 47 |
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#define AT_VECTOR_SIZE_ARCH 14 /* entries in ARCH_DLINFO */ |
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#endif
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