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459 lines
10 KiB
459 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPC8377E WLAN Device Tree Source |
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* |
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* Copyright 2007-2009 Freescale Semiconductor Inc. |
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* Copyright 2009 MontaVista Software, Inc. |
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*/ |
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/dts-v1/; |
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/ { |
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compatible = "fsl,mpc8377wlan"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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aliases { |
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ethernet0 = &enet0; |
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ethernet1 = &enet1; |
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serial0 = &serial0; |
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serial1 = &serial1; |
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pci0 = &pci0; |
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pci1 = &pci1; |
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pci2 = &pci2; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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PowerPC,8377@0 { |
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device_type = "cpu"; |
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reg = <0x0>; |
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d-cache-line-size = <32>; |
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i-cache-line-size = <32>; |
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d-cache-size = <32768>; |
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i-cache-size = <32768>; |
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timebase-frequency = <0>; |
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bus-frequency = <0>; |
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clock-frequency = <0>; |
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}; |
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}; |
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memory { |
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device_type = "memory"; |
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reg = <0x00000000 0x20000000>; // 512MB at 0 |
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}; |
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localbus@e0005000 { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus"; |
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reg = <0xe0005000 0x1000>; |
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interrupts = <77 0x8>; |
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interrupt-parent = <&ipic>; |
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ranges = <0x0 0x0 0xfc000000 0x04000000>; |
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flash@0,0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "cfi-flash"; |
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reg = <0x0 0x0 0x4000000>; |
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bank-width = <2>; |
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device-width = <1>; |
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partition@0 { |
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reg = <0 0x80000>; |
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label = "u-boot"; |
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read-only; |
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}; |
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partition@a0000 { |
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reg = <0xa0000 0x300000>; |
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label = "kernel"; |
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}; |
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partition@3a0000 { |
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reg = <0x3a0000 0x3c60000>; |
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label = "rootfs"; |
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}; |
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}; |
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}; |
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immr@e0000000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "simple-bus"; |
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ranges = <0x0 0xe0000000 0x00100000>; |
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reg = <0xe0000000 0x00000200>; |
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bus-frequency = <0>; |
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wdt@200 { |
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device_type = "watchdog"; |
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compatible = "mpc83xx_wdt"; |
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reg = <0x200 0x100>; |
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}; |
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gpio1: gpio-controller@c00 { |
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#gpio-cells = <2>; |
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compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; |
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reg = <0xc00 0x100>; |
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interrupts = <74 0x8>; |
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interrupt-parent = <&ipic>; |
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gpio-controller; |
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}; |
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gpio2: gpio-controller@d00 { |
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#gpio-cells = <2>; |
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compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio"; |
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reg = <0xd00 0x100>; |
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interrupts = <75 0x8>; |
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interrupt-parent = <&ipic>; |
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gpio-controller; |
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}; |
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sleep-nexus { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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sleep = <&pmc 0x0c000000>; |
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ranges; |
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i2c@3000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <0>; |
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compatible = "fsl-i2c"; |
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reg = <0x3000 0x100>; |
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interrupts = <14 0x8>; |
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interrupt-parent = <&ipic>; |
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dfsrr; |
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at24@50 { |
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compatible = "atmel,24c256"; |
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reg = <0x50>; |
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}; |
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rtc@68 { |
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compatible = "dallas,ds1339"; |
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reg = <0x68>; |
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}; |
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}; |
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sdhci@2e000 { |
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compatible = "fsl,mpc8377-esdhc", "fsl,esdhc"; |
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reg = <0x2e000 0x1000>; |
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interrupts = <42 0x8>; |
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interrupt-parent = <&ipic>; |
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sdhci,wp-inverted; |
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clock-frequency = <133333333>; |
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}; |
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}; |
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i2c@3100 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <1>; |
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compatible = "fsl-i2c"; |
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reg = <0x3100 0x100>; |
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interrupts = <15 0x8>; |
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interrupt-parent = <&ipic>; |
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dfsrr; |
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}; |
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spi@7000 { |
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cell-index = <0>; |
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compatible = "fsl,spi"; |
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reg = <0x7000 0x1000>; |
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interrupts = <16 0x8>; |
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interrupt-parent = <&ipic>; |
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mode = "cpu"; |
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}; |
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dma@82a8 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8377-dma", "fsl,elo-dma"; |
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reg = <0x82a8 4>; |
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ranges = <0 0x8100 0x1a8>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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cell-index = <0>; |
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dma-channel@0 { |
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compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0 0x80>; |
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cell-index = <0>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@80 { |
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compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x80 0x80>; |
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cell-index = <1>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@100 { |
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compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x100 0x80>; |
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cell-index = <2>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@180 { |
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compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x180 0x28>; |
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cell-index = <3>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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}; |
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usb@23000 { |
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compatible = "fsl-usb2-dr"; |
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reg = <0x23000 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupt-parent = <&ipic>; |
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interrupts = <38 0x8>; |
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phy_type = "ulpi"; |
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sleep = <&pmc 0x00c00000>; |
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}; |
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enet0: ethernet@24000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cell-index = <0>; |
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device_type = "network"; |
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model = "eTSEC"; |
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compatible = "gianfar"; |
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reg = <0x24000 0x1000>; |
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ranges = <0x0 0x24000 0x1000>; |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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interrupts = <32 0x8 33 0x8 34 0x8>; |
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phy-connection-type = "mii"; |
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interrupt-parent = <&ipic>; |
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tbi-handle = <&tbi0>; |
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phy-handle = <&phy2>; |
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sleep = <&pmc 0xc0000000>; |
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fsl,magic-packet; |
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mdio@520 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,gianfar-mdio"; |
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reg = <0x520 0x20>; |
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phy2: ethernet-phy@2 { |
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interrupt-parent = <&ipic>; |
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interrupts = <17 0x8>; |
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reg = <0x2>; |
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}; |
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phy3: ethernet-phy@3 { |
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interrupt-parent = <&ipic>; |
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interrupts = <18 0x8>; |
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reg = <0x3>; |
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}; |
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tbi0: tbi-phy@11 { |
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reg = <0x11>; |
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device_type = "tbi-phy"; |
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}; |
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}; |
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}; |
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enet1: ethernet@25000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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cell-index = <1>; |
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device_type = "network"; |
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model = "eTSEC"; |
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compatible = "gianfar"; |
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reg = <0x25000 0x1000>; |
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ranges = <0x0 0x25000 0x1000>; |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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interrupts = <35 0x8 36 0x8 37 0x8>; |
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phy-connection-type = "mii"; |
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interrupt-parent = <&ipic>; |
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phy-handle = <&phy3>; |
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tbi-handle = <&tbi1>; |
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sleep = <&pmc 0x30000000>; |
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fsl,magic-packet; |
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mdio@520 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,gianfar-tbi"; |
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reg = <0x520 0x20>; |
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tbi1: tbi-phy@11 { |
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reg = <0x11>; |
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device_type = "tbi-phy"; |
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}; |
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}; |
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}; |
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serial0: serial@4500 { |
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cell-index = <0>; |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550"; |
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reg = <0x4500 0x100>; |
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clock-frequency = <0>; |
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interrupts = <9 0x8>; |
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interrupt-parent = <&ipic>; |
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}; |
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serial1: serial@4600 { |
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cell-index = <1>; |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550"; |
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reg = <0x4600 0x100>; |
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clock-frequency = <0>; |
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interrupts = <10 0x8>; |
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interrupt-parent = <&ipic>; |
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}; |
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crypto@30000 { |
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", |
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"fsl,sec2.1", "fsl,sec2.0"; |
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reg = <0x30000 0x10000>; |
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interrupts = <11 0x8>; |
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interrupt-parent = <&ipic>; |
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fsl,num-channels = <4>; |
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fsl,channel-fifo-len = <24>; |
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fsl,exec-units-mask = <0x9fe>; |
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fsl,descriptor-types-mask = <0x3ab0ebf>; |
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sleep = <&pmc 0x03000000>; |
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}; |
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sata@18000 { |
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compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; |
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reg = <0x18000 0x1000>; |
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interrupts = <44 0x8>; |
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interrupt-parent = <&ipic>; |
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sleep = <&pmc 0x000000c0>; |
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}; |
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sata@19000 { |
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compatible = "fsl,mpc8377-sata", "fsl,pq-sata"; |
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reg = <0x19000 0x1000>; |
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interrupts = <45 0x8>; |
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interrupt-parent = <&ipic>; |
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sleep = <&pmc 0x00000030>; |
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}; |
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/* IPIC |
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* interrupts cell = <intr #, sense> |
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* sense values match linux IORESOURCE_IRQ_* defines: |
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* sense == 8: Level, low assertion |
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* sense == 2: Edge, high-to-low change |
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*/ |
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ipic: interrupt-controller@700 { |
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compatible = "fsl,ipic"; |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <2>; |
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reg = <0x700 0x100>; |
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}; |
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pmc: power@b00 { |
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compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc"; |
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reg = <0xb00 0x100 0xa00 0x100>; |
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interrupts = <80 0x8>; |
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interrupt-parent = <&ipic>; |
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}; |
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}; |
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pci0: pci@e0008500 { |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = < |
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/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */ |
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/* IDSEL AD14 IRQ6 inta */ |
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0x7000 0x0 0x0 0x1 &ipic 22 0x8 |
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/* IDSEL AD15 IRQ5 inta */ |
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0x7800 0x0 0x0 0x1 &ipic 21 0x8>; |
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interrupt-parent = <&ipic>; |
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interrupts = <66 0x8>; |
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bus-range = <0 0>; |
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 |
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 |
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0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>; |
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sleep = <&pmc 0x00010000>; |
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clock-frequency = <66666666>; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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reg = <0xe0008500 0x100 /* internal registers */ |
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0xe0008300 0x8>; /* config space access registers */ |
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compatible = "fsl,mpc8349-pci"; |
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device_type = "pci"; |
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}; |
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pci1: pcie@e0009000 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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device_type = "pci"; |
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compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; |
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reg = <0xe0009000 0x00001000>; |
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ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000 |
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0x01000000 0 0x00000000 0xb8000000 0 0x00800000>; |
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bus-range = <0 255>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = <0 0 0 1 &ipic 1 8 |
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0 0 0 2 &ipic 1 8 |
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0 0 0 3 &ipic 1 8 |
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0 0 0 4 &ipic 1 8>; |
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sleep = <&pmc 0x00300000>; |
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clock-frequency = <0>; |
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pcie@0 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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device_type = "pci"; |
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reg = <0 0 0 0 0>; |
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ranges = <0x02000000 0 0xa8000000 |
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0x02000000 0 0xa8000000 |
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0 0x10000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00800000>; |
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}; |
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}; |
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pci2: pcie@e000a000 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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device_type = "pci"; |
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compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie"; |
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reg = <0xe000a000 0x00001000>; |
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ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000 |
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0x01000000 0 0x00000000 0xd8000000 0 0x00800000>; |
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bus-range = <0 255>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = <0 0 0 1 &ipic 2 8 |
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0 0 0 2 &ipic 2 8 |
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0 0 0 3 &ipic 2 8 |
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0 0 0 4 &ipic 2 8>; |
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sleep = <&pmc 0x000c0000>; |
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clock-frequency = <0>; |
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pcie@0 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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device_type = "pci"; |
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reg = <0 0 0 0 0>; |
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ranges = <0x02000000 0 0xc8000000 |
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0x02000000 0 0xc8000000 |
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0 0x10000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00800000>; |
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}; |
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}; |
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};
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