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363 lines
7.9 KiB
363 lines
7.9 KiB
/* |
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* T4240RDB Device Tree Source |
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* |
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* Copyright 2014 - 2015 Freescale Semiconductor Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/include/ "t4240si-pre.dtsi" |
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/ { |
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model = "fsl,T4240RDB"; |
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compatible = "fsl,T4240RDB"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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aliases { |
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sgmii_phy21 = &sgmiiphy21; |
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sgmii_phy22 = &sgmiiphy22; |
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sgmii_phy23 = &sgmiiphy23; |
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sgmii_phy24 = &sgmiiphy24; |
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sgmii_phy41 = &sgmiiphy41; |
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sgmii_phy42 = &sgmiiphy42; |
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sgmii_phy43 = &sgmiiphy43; |
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sgmii_phy44 = &sgmiiphy44; |
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}; |
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ifc: localbus@ffe124000 { |
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reg = <0xf 0xfe124000 0 0x2000>; |
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ranges = <0 0 0xf 0xe8000000 0x08000000 |
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2 0 0xf 0xff800000 0x00010000 |
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3 0 0xf 0xffdf0000 0x00008000>; |
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nor@0,0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "cfi-flash"; |
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reg = <0x0 0x0 0x8000000>; |
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bank-width = <2>; |
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device-width = <1>; |
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}; |
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nand@2,0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,ifc-nand"; |
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reg = <0x2 0x0 0x10000>; |
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}; |
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}; |
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memory { |
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device_type = "memory"; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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bman_fbpr: bman-fbpr { |
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size = <0 0x1000000>; |
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alignment = <0 0x1000000>; |
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}; |
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qman_fqd: qman-fqd { |
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size = <0 0x400000>; |
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alignment = <0 0x400000>; |
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}; |
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qman_pfdr: qman-pfdr { |
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size = <0 0x2000000>; |
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alignment = <0 0x2000000>; |
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}; |
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}; |
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dcsr: dcsr@f00000000 { |
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ranges = <0x00000000 0xf 0x00000000 0x01072000>; |
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}; |
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bportals: bman-portals@ff4000000 { |
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ranges = <0x0 0xf 0xf4000000 0x2000000>; |
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}; |
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qportals: qman-portals@ff6000000 { |
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ranges = <0x0 0xf 0xf6000000 0x2000000>; |
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}; |
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soc: soc@ffe000000 { |
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
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reg = <0xf 0xfe000000 0 0x00001000>; |
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spi@110000 { |
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flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "sst,sst25wf040", "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <40000000>; /* input clock */ |
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}; |
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}; |
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i2c@118000 { |
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hwmon@2f { |
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compatible = "winbond,w83793"; |
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reg = <0x2f>; |
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}; |
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eeprom@52 { |
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compatible = "atmel,24c256"; |
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reg = <0x52>; |
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}; |
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eeprom@54 { |
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compatible = "atmel,24c256"; |
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reg = <0x54>; |
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}; |
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eeprom@56 { |
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compatible = "atmel,24c256"; |
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reg = <0x56>; |
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}; |
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rtc@68 { |
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compatible = "dallas,ds1374"; |
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reg = <0x68>; |
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}; |
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}; |
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sdhc@114000 { |
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voltage-ranges = <1800 1800 3300 3300>; |
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}; |
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fman@400000 { |
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ethernet@e0000 { |
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phy-handle = <&sgmiiphy21>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e2000 { |
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phy-handle = <&sgmiiphy22>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e4000 { |
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phy-handle = <&sgmiiphy23>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e6000 { |
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phy-handle = <&sgmiiphy24>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e8000 { |
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status = "disabled"; |
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}; |
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ethernet@ea000 { |
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status = "disabled"; |
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}; |
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ethernet@f0000 { |
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phy-handle = <&xfiphy1>; |
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phy-connection-type = "xgmii"; |
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}; |
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ethernet@f2000 { |
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phy-handle = <&xfiphy2>; |
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phy-connection-type = "xgmii"; |
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}; |
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}; |
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fman@500000 { |
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ethernet@e0000 { |
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phy-handle = <&sgmiiphy41>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e2000 { |
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phy-handle = <&sgmiiphy42>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e4000 { |
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phy-handle = <&sgmiiphy43>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e6000 { |
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phy-handle = <&sgmiiphy44>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e8000 { |
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status = "disabled"; |
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}; |
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ethernet@ea000 { |
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status = "disabled"; |
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}; |
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ethernet@f0000 { |
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phy-handle = <&xfiphy3>; |
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phy-connection-type = "xgmii"; |
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}; |
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ethernet@f2000 { |
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phy-handle = <&xfiphy4>; |
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phy-connection-type = "xgmii"; |
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}; |
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mdio@fc000 { |
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sgmiiphy21: ethernet-phy@0 { |
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reg = <0x0>; |
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}; |
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sgmiiphy22: ethernet-phy@1 { |
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reg = <0x1>; |
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}; |
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sgmiiphy23: ethernet-phy@2 { |
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reg = <0x2>; |
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}; |
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sgmiiphy24: ethernet-phy@3 { |
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reg = <0x3>; |
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}; |
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sgmiiphy41: ethernet-phy@4 { |
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reg = <0x4>; |
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}; |
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sgmiiphy42: ethernet-phy@5 { |
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reg = <0x5>; |
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}; |
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sgmiiphy43: ethernet-phy@6 { |
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reg = <0x6>; |
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}; |
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sgmiiphy44: ethernet-phy@7 { |
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reg = <0x7>; |
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}; |
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}; |
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mdio@fd000 { |
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xfiphy1: ethernet-phy@10 { |
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compatible = "ethernet-phy-id13e5.1002"; |
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reg = <0x10>; |
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}; |
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xfiphy2: ethernet-phy@11 { |
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compatible = "ethernet-phy-id13e5.1002"; |
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reg = <0x11>; |
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}; |
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xfiphy3: ethernet-phy@13 { |
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compatible = "ethernet-phy-id13e5.1002"; |
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reg = <0x13>; |
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}; |
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xfiphy4: ethernet-phy@12 { |
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compatible = "ethernet-phy-id13e5.1002"; |
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reg = <0x12>; |
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}; |
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}; |
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}; |
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}; |
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pci0: pcie@ffe240000 { |
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reg = <0xf 0xfe240000 0 0x10000>; |
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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pci1: pcie@ffe250000 { |
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reg = <0xf 0xfe250000 0 0x10000>; |
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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pci2: pcie@ffe260000 { |
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reg = <0xf 0xfe260000 0 0x1000>; |
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ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 |
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0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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pci3: pcie@ffe270000 { |
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reg = <0xf 0xfe270000 0 0x10000>; |
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ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 |
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0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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rio: rapidio@ffe0c0000 { |
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reg = <0xf 0xfe0c0000 0 0x11000>; |
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port1 { |
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ranges = <0 0 0xc 0x20000000 0 0x10000000>; |
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}; |
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port2 { |
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ranges = <0 0 0xc 0x30000000 0 0x10000000>; |
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}; |
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}; |
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}; |
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/include/ "t4240si-post.dtsi"
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