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196 lines
5.3 KiB
196 lines
5.3 KiB
/* |
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* MPC8572 Silicon/SoC Device Tree Source (post include) |
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* |
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* Copyright 2011 Freescale Semiconductor Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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&lbc { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; |
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interrupts = <19 2 0 0>; |
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}; |
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/* controller at 0x8000 */ |
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&pci0 { |
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compatible = "fsl,mpc8548-pcie"; |
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device_type = "pci"; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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bus-range = <0 255>; |
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clock-frequency = <33333333>; |
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interrupts = <24 2 0 0>; |
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pcie@0 { |
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reg = <0 0 0 0 0>; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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device_type = "pci"; |
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interrupts = <24 2 0 0>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = < |
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/* IDSEL 0x0 */ |
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0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 |
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0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 |
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0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 |
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0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 |
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>; |
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}; |
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}; |
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/* controller at 0x9000 */ |
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&pci1 { |
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compatible = "fsl,mpc8548-pcie"; |
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device_type = "pci"; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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bus-range = <0 255>; |
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clock-frequency = <33333333>; |
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interrupts = <25 2 0 0>; |
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pcie@0 { |
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reg = <0 0 0 0 0>; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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device_type = "pci"; |
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interrupts = <25 2 0 0>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = < |
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/* IDSEL 0x0 */ |
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0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 |
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0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 |
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0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 |
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0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 |
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>; |
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}; |
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}; |
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/* controller at 0xa000 */ |
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&pci2 { |
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compatible = "fsl,mpc8548-pcie"; |
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device_type = "pci"; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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bus-range = <0 255>; |
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clock-frequency = <33333333>; |
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interrupts = <26 2 0 0>; |
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pcie@0 { |
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reg = <0 0 0 0 0>; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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device_type = "pci"; |
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interrupts = <26 2 0 0>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = < |
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/* IDSEL 0x0 */ |
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 |
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 |
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 |
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 |
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>; |
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}; |
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}; |
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&soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "fsl,mpc8572-immr", "simple-bus"; |
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bus-frequency = <0>; // Filled out by uboot. |
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ecm-law@0 { |
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compatible = "fsl,ecm-law"; |
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reg = <0x0 0x1000>; |
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fsl,num-laws = <12>; |
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}; |
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ecm@1000 { |
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compatible = "fsl,mpc8572-ecm", "fsl,ecm"; |
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reg = <0x1000 0x1000>; |
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interrupts = <17 2 0 0>; |
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}; |
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memory-controller@2000 { |
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compatible = "fsl,mpc8572-memory-controller"; |
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reg = <0x2000 0x1000>; |
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interrupts = <18 2 0 0>; |
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}; |
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memory-controller@6000 { |
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compatible = "fsl,mpc8572-memory-controller"; |
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reg = <0x6000 0x1000>; |
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interrupts = <18 2 0 0>; |
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}; |
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/include/ "pq3-i2c-0.dtsi" |
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/include/ "pq3-i2c-1.dtsi" |
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/include/ "pq3-duart-0.dtsi" |
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/include/ "pq3-dma-1.dtsi" |
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/include/ "pq3-gpio-0.dtsi" |
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gpio-controller@f000 { |
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compatible = "fsl,mpc8572-gpio"; |
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}; |
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L2: l2-cache-controller@20000 { |
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compatible = "fsl,mpc8572-l2-cache-controller"; |
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reg = <0x20000 0x1000>; |
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cache-line-size = <32>; // 32 bytes |
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cache-size = <0x100000>; // L2,1M |
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interrupts = <16 2 0 0>; |
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}; |
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/include/ "pq3-dma-0.dtsi" |
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/include/ "pq3-etsec1-0.dtsi" |
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/include/ "pq3-etsec1-timer-0.dtsi" |
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ptp_clock@24e00 { |
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interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>; |
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}; |
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/include/ "pq3-etsec1-1.dtsi" |
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/include/ "pq3-etsec1-2.dtsi" |
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/include/ "pq3-etsec1-3.dtsi" |
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/include/ "pq3-sec3.0-0.dtsi" |
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/include/ "pq3-mpic.dtsi" |
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/include/ "pq3-mpic-timer-B.dtsi" |
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global-utilities@e0000 { |
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compatible = "fsl,mpc8572-guts"; |
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reg = <0xe0000 0x1000>; |
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fsl,has-rstcr; |
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}; |
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};
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