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304 lines
6.9 KiB
304 lines
6.9 KiB
/* |
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* MPC8569 Silicon/SoC Device Tree Source (post include) |
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* |
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* Copyright 2011 Freescale Semiconductor Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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&lbc { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus"; |
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interrupts = <19 2 0 0>; |
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sleep = <&pmc 0x08000000>; |
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}; |
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/* controller at 0xa000 */ |
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&pci1 { |
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compatible = "fsl,mpc8548-pcie"; |
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device_type = "pci"; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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bus-range = <0 255>; |
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clock-frequency = <33333333>; |
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interrupts = <26 2 0 0>; |
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sleep = <&pmc 0x20000000>; |
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pcie@0 { |
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reg = <0 0 0 0 0>; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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device_type = "pci"; |
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interrupts = <26 2 0 0>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = < |
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/* IDSEL 0x0 */ |
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 |
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 |
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 |
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 |
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>; |
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}; |
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}; |
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&rio { |
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compatible = "fsl,srio"; |
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interrupts = <48 2 0 0>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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fsl,srio-rmu-handle = <&rmu>; |
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sleep = <&pmc 0x00080000>; |
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ranges; |
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port1 { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cell-index = <1>; |
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}; |
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port2 { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cell-index = <2>; |
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}; |
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}; |
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&soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "fsl,mpc8569-immr", "simple-bus"; |
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bus-frequency = <0>; // Filled out by uboot. |
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ecm-law@0 { |
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compatible = "fsl,ecm-law"; |
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reg = <0x0 0x1000>; |
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fsl,num-laws = <10>; |
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}; |
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ecm@1000 { |
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compatible = "fsl,mpc8569-ecm", "fsl,ecm"; |
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reg = <0x1000 0x1000>; |
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interrupts = <17 2 0 0>; |
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}; |
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memory-controller@2000 { |
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compatible = "fsl,mpc8569-memory-controller"; |
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reg = <0x2000 0x1000>; |
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interrupts = <18 2 0 0>; |
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}; |
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i2c-sleep-nexus { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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sleep = <&pmc 0x00000004>; |
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ranges; |
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/include/ "pq3-i2c-0.dtsi" |
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/include/ "pq3-i2c-1.dtsi" |
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}; |
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duart-sleep-nexus { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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sleep = <&pmc 0x00000002>; |
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ranges; |
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/include/ "pq3-duart-0.dtsi" |
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}; |
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L2: l2-cache-controller@20000 { |
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compatible = "fsl,mpc8569-l2-cache-controller"; |
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reg = <0x20000 0x1000>; |
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cache-line-size = <32>; // 32 bytes |
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cache-size = <0x80000>; // L2, 512K |
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interrupts = <16 2 0 0>; |
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}; |
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/include/ "pq3-dma-0.dtsi" |
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/include/ "pq3-esdhc-0.dtsi" |
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sdhc@2e000 { |
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sleep = <&pmc 0x00200000>; |
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}; |
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par_io@e0100 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0xe0100 0x100>; |
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ranges = <0x0 0xe0100 0x100>; |
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device_type = "par_io"; |
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}; |
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/include/ "pq3-sec3.1-0.dtsi" |
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crypto@30000 { |
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sleep = <&pmc 0x01000000>; |
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}; |
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/include/ "pq3-mpic.dtsi" |
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/include/ "pq3-rmu-0.dtsi" |
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rmu@d3000 { |
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sleep = <&pmc 0x00040000>; |
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}; |
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global-utilities@e0000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8569-guts", "fsl,mpc8548-guts"; |
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reg = <0xe0000 0x1000>; |
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ranges = <0 0xe0000 0x1000>; |
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fsl,has-rstcr; |
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pmc: power@70 { |
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compatible = "fsl,mpc8569-pmc", |
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"fsl,mpc8548-pmc"; |
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reg = <0x70 0x20>; |
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}; |
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}; |
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}; |
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&qe { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "qe"; |
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compatible = "fsl,qe"; |
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sleep = <&pmc 0x00000800>; |
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brg-frequency = <0>; |
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bus-frequency = <0>; |
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fsl,qe-num-riscs = <4>; |
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fsl,qe-num-snums = <46>; |
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qeic: interrupt-controller@80 { |
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interrupt-controller; |
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compatible = "fsl,qe-ic"; |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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reg = <0x80 0x80>; |
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interrupts = <46 2 0 0 46 2 0 0>; //high:30 low:30 |
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interrupt-parent = <&mpic>; |
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}; |
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timer@440 { |
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compatible = "fsl,mpc8569-qe-gtm", |
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"fsl,qe-gtm", "fsl,gtm"; |
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reg = <0x440 0x40>; |
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interrupts = <12 13 14 15>; |
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interrupt-parent = <&qeic>; |
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/* Filled in by U-Boot */ |
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clock-frequency = <0>; |
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}; |
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spi@4c0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,mpc8569-qe-spi", "fsl,spi"; |
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reg = <0x4c0 0x40>; |
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cell-index = <0>; |
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interrupts = <2>; |
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interrupt-parent = <&qeic>; |
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}; |
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spi@500 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <1>; |
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compatible = "fsl,spi"; |
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reg = <0x500 0x40>; |
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interrupts = <1>; |
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interrupt-parent = <&qeic>; |
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}; |
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usb@6c0 { |
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compatible = "fsl,mpc8569-qe-usb", |
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"fsl,mpc8323-qe-usb"; |
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reg = <0x6c0 0x40 0x8b00 0x100>; |
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interrupts = <11>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@2000 { |
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cell-index = <1>; |
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reg = <0x2000 0x200>; |
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interrupts = <32>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@2200 { |
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cell-index = <3>; |
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reg = <0x2200 0x200>; |
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interrupts = <34>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@3000 { |
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cell-index = <2>; |
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reg = <0x3000 0x200>; |
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interrupts = <33>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@3200 { |
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cell-index = <4>; |
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reg = <0x3200 0x200>; |
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interrupts = <35>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@3400 { |
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cell-index = <6>; |
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reg = <0x3400 0x200>; |
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interrupts = <41>; |
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interrupt-parent = <&qeic>; |
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}; |
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ucc@3600 { |
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cell-index = <8>; |
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reg = <0x3600 0x200>; |
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interrupts = <43>; |
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interrupt-parent = <&qeic>; |
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}; |
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muram@10000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
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ranges = <0x0 0x10000 0x20000>; |
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data-only@0 { |
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compatible = "fsl,qe-muram-data", |
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"fsl,cpm-muram-data"; |
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reg = <0x0 0x20000>; |
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}; |
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}; |
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};
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