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185 lines
5.7 KiB
185 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* asm/dma.h: Defines for using and allocating dma channels. |
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* Written by Hennus Bergman, 1992. |
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* High DMA channel support & info by Hannu Savolainen |
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* and John Boyd, Nov. 1992. |
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* (c) Copyright 2000, Grant Grundler |
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*/ |
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#ifndef _ASM_DMA_H |
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#define _ASM_DMA_H |
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#include <asm/io.h> /* need byte IO */ |
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#define dma_outb outb |
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#define dma_inb inb |
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/* |
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** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up |
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** (or rather not merge) DMAs into manageable chunks. |
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** On parisc, this is more of the software/tuning constraint |
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** rather than the HW. I/O MMU allocation algorithms can be |
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** faster with smaller sizes (to some degree). |
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*/ |
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#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE) |
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/* The maximum address that we can perform a DMA transfer to on this platform |
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** New dynamic DMA interfaces should obsolete this.... |
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*/ |
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#define MAX_DMA_ADDRESS (~0UL) |
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/* |
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** We don't have DMA channels... well V-class does but the |
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** Dynamic DMA Mapping interface will support them... right? :^) |
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** Note: this is not relevant right now for PA-RISC, but we cannot |
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** leave this as undefined because some things (e.g. sound) |
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** won't compile :-( |
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*/ |
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#define MAX_DMA_CHANNELS 8 |
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#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
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#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
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#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
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#define DMA_AUTOINIT 0x10 |
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/* 8237 DMA controllers */ |
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#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
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#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ |
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/* DMA controller registers */ |
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#define DMA1_CMD_REG 0x08 /* command register (w) */ |
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#define DMA1_STAT_REG 0x08 /* status register (r) */ |
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#define DMA1_REQ_REG 0x09 /* request register (w) */ |
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#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ |
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#define DMA1_MODE_REG 0x0B /* mode register (w) */ |
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#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
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#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ |
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#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
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#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ |
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#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ |
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#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) |
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#define DMA2_CMD_REG 0xD0 /* command register (w) */ |
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#define DMA2_STAT_REG 0xD0 /* status register (r) */ |
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#define DMA2_REQ_REG 0xD2 /* request register (w) */ |
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#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
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#define DMA2_MODE_REG 0xD6 /* mode register (w) */ |
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#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
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#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ |
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#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
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#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ |
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#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ |
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#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) |
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static __inline__ unsigned long claim_dma_lock(void) |
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{ |
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return 0; |
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} |
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static __inline__ void release_dma_lock(unsigned long flags) |
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{ |
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} |
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/* Get DMA residue count. After a DMA transfer, this |
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* should return zero. Reading this while a DMA transfer is |
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* still in progress will return unpredictable results. |
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* If called before the channel has been used, it may return 1. |
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* Otherwise, it returns the number of _bytes_ left to transfer. |
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* |
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* Assumes DMA flip-flop is clear. |
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*/ |
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static __inline__ int get_dma_residue(unsigned int dmanr) |
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{ |
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unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE |
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: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; |
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/* using short to get 16-bit wrap around */ |
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unsigned short count; |
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count = 1 + dma_inb(io_port); |
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count += dma_inb(io_port) << 8; |
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return (dmanr<=3)? count : (count<<1); |
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} |
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/* enable/disable a specific DMA channel */ |
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static __inline__ void enable_dma(unsigned int dmanr) |
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{ |
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#ifdef CONFIG_SUPERIO |
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if (dmanr<=3) |
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dma_outb(dmanr, DMA1_MASK_REG); |
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else |
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dma_outb(dmanr & 3, DMA2_MASK_REG); |
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#endif |
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} |
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static __inline__ void disable_dma(unsigned int dmanr) |
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{ |
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#ifdef CONFIG_SUPERIO |
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if (dmanr<=3) |
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dma_outb(dmanr | 4, DMA1_MASK_REG); |
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else |
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dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); |
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#endif |
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} |
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/* reserve a DMA channel */ |
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#define request_dma(dmanr, device_id) (0) |
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/* Clear the 'DMA Pointer Flip Flop'. |
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* Write 0 for LSB/MSB, 1 for MSB/LSB access. |
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* Use this once to initialize the FF to a known state. |
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* After that, keep track of it. :-) |
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* --- In order to do that, the DMA routines below should --- |
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* --- only be used while holding the DMA lock ! --- |
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*/ |
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static __inline__ void clear_dma_ff(unsigned int dmanr) |
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{ |
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} |
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/* set mode (above) for a specific DMA channel */ |
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static __inline__ void set_dma_mode(unsigned int dmanr, char mode) |
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{ |
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} |
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/* Set only the page register bits of the transfer address. |
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* This is used for successive transfers when we know the contents of |
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* the lower 16 bits of the DMA current address register, but a 64k boundary |
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* may have been crossed. |
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*/ |
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static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) |
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{ |
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} |
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/* Set transfer address & page bits for specific DMA channel. |
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* Assumes dma flipflop is clear. |
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*/ |
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static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) |
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{ |
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} |
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/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for |
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* a specific DMA channel. |
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* You must ensure the parameters are valid. |
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* NOTE: from a manual: "the number of transfers is one more |
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* than the initial word count"! This is taken into account. |
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* Assumes dma flip-flop is clear. |
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* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. |
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*/ |
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static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) |
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{ |
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} |
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#define free_dma(dmanr) |
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#ifdef CONFIG_PCI |
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extern int isa_dma_bridge_buggy; |
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#else |
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#define isa_dma_bridge_buggy (0) |
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#endif |
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#endif /* _ASM_DMA_H */
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