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97 lines
2.5 KiB
97 lines
2.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ASM_BARRIER_H |
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#define __ASM_BARRIER_H |
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#include <asm/alternative.h> |
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#ifndef __ASSEMBLY__ |
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/* The synchronize caches instruction executes as a nop on systems in |
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which all memory references are performed in order. */ |
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#define synchronize_caches() asm volatile("sync" \ |
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ALTERNATIVE(ALT_COND_NO_SMP, INSN_NOP) \ |
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: : : "memory") |
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#if defined(CONFIG_SMP) |
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#define mb() do { synchronize_caches(); } while (0) |
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#define rmb() mb() |
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#define wmb() mb() |
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#define dma_rmb() mb() |
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#define dma_wmb() mb() |
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#else |
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#define mb() barrier() |
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#define rmb() barrier() |
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#define wmb() barrier() |
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#define dma_rmb() barrier() |
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#define dma_wmb() barrier() |
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#endif |
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#define __smp_mb() mb() |
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#define __smp_rmb() mb() |
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#define __smp_wmb() mb() |
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#define __smp_store_release(p, v) \ |
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do { \ |
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typeof(p) __p = (p); \ |
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union { typeof(*p) __val; char __c[1]; } __u = \ |
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{ .__val = (__force typeof(*p)) (v) }; \ |
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compiletime_assert_atomic_type(*p); \ |
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switch (sizeof(*p)) { \ |
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case 1: \ |
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asm volatile("stb,ma %0,0(%1)" \ |
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: : "r"(*(__u8 *)__u.__c), "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 2: \ |
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asm volatile("sth,ma %0,0(%1)" \ |
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: : "r"(*(__u16 *)__u.__c), "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 4: \ |
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asm volatile("stw,ma %0,0(%1)" \ |
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: : "r"(*(__u32 *)__u.__c), "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 8: \ |
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if (IS_ENABLED(CONFIG_64BIT)) \ |
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asm volatile("std,ma %0,0(%1)" \ |
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: : "r"(*(__u64 *)__u.__c), "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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} \ |
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} while (0) |
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#define __smp_load_acquire(p) \ |
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({ \ |
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union { typeof(*p) __val; char __c[1]; } __u; \ |
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typeof(p) __p = (p); \ |
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compiletime_assert_atomic_type(*p); \ |
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switch (sizeof(*p)) { \ |
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case 1: \ |
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asm volatile("ldb,ma 0(%1),%0" \ |
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: "=r"(*(__u8 *)__u.__c) : "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 2: \ |
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asm volatile("ldh,ma 0(%1),%0" \ |
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: "=r"(*(__u16 *)__u.__c) : "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 4: \ |
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asm volatile("ldw,ma 0(%1),%0" \ |
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: "=r"(*(__u32 *)__u.__c) : "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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case 8: \ |
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if (IS_ENABLED(CONFIG_64BIT)) \ |
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asm volatile("ldd,ma 0(%1),%0" \ |
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: "=r"(*(__u64 *)__u.__c) : "r"(__p) \ |
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: "memory"); \ |
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break; \ |
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} \ |
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__u.__val; \ |
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}) |
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#include <asm-generic/barrier.h> |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* __ASM_BARRIER_H */
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