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229 lines
5.5 KiB
229 lines
5.5 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (C) 2000 Philipp Rumpf <[email protected]> |
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* Copyright (C) 2006 Kyle McMartin <[email protected]> |
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*/ |
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#ifndef _ASM_PARISC_ATOMIC_H_ |
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#define _ASM_PARISC_ATOMIC_H_ |
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#include <linux/types.h> |
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#include <asm/cmpxchg.h> |
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#include <asm/barrier.h> |
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/* |
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* Atomic operations that C can't guarantee us. Useful for |
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* resource counting etc.. |
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* |
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* And probably incredibly slow on parisc. OTOH, we don't |
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* have to write any serious assembly. prumpf |
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*/ |
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#ifdef CONFIG_SMP |
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#include <asm/spinlock.h> |
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#include <asm/cache.h> /* we use L1_CACHE_BYTES */ |
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/* Use an array of spinlocks for our atomic_ts. |
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* Hash function to index into a different SPINLOCK. |
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* Since "a" is usually an address, use one spinlock per cacheline. |
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*/ |
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# define ATOMIC_HASH_SIZE 4 |
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# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) |
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extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; |
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/* Can't use raw_spin_lock_irq because of #include problems, so |
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* this is the substitute */ |
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#define _atomic_spin_lock_irqsave(l,f) do { \ |
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arch_spinlock_t *s = ATOMIC_HASH(l); \ |
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local_irq_save(f); \ |
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arch_spin_lock(s); \ |
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} while(0) |
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#define _atomic_spin_unlock_irqrestore(l,f) do { \ |
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arch_spinlock_t *s = ATOMIC_HASH(l); \ |
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arch_spin_unlock(s); \ |
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local_irq_restore(f); \ |
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} while(0) |
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#else |
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# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) |
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# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) |
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#endif |
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/* |
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* Note that we need not lock read accesses - aligned word writes/reads |
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* are atomic, so a reader never sees inconsistent values. |
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*/ |
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static __inline__ void atomic_set(atomic_t *v, int i) |
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{ |
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unsigned long flags; |
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_atomic_spin_lock_irqsave(v, flags); |
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v->counter = i; |
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_atomic_spin_unlock_irqrestore(v, flags); |
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} |
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#define atomic_set_release(v, i) atomic_set((v), (i)) |
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static __inline__ int atomic_read(const atomic_t *v) |
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{ |
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return READ_ONCE((v)->counter); |
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} |
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/* exported interface */ |
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n))) |
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) |
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#define ATOMIC_OP(op, c_op) \ |
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static __inline__ void atomic_##op(int i, atomic_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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v->counter c_op i; \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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} |
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#define ATOMIC_OP_RETURN(op, c_op) \ |
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static __inline__ int atomic_##op##_return(int i, atomic_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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int ret; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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ret = (v->counter c_op i); \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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\ |
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return ret; \ |
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} |
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#define ATOMIC_FETCH_OP(op, c_op) \ |
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static __inline__ int atomic_fetch_##op(int i, atomic_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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int ret; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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ret = v->counter; \ |
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v->counter c_op i; \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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\ |
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return ret; \ |
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} |
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#define ATOMIC_OPS(op, c_op) \ |
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ATOMIC_OP(op, c_op) \ |
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ATOMIC_OP_RETURN(op, c_op) \ |
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ATOMIC_FETCH_OP(op, c_op) |
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ATOMIC_OPS(add, +=) |
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ATOMIC_OPS(sub, -=) |
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#undef ATOMIC_OPS |
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#define ATOMIC_OPS(op, c_op) \ |
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ATOMIC_OP(op, c_op) \ |
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ATOMIC_FETCH_OP(op, c_op) |
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ATOMIC_OPS(and, &=) |
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ATOMIC_OPS(or, |=) |
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ATOMIC_OPS(xor, ^=) |
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#undef ATOMIC_OPS |
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#undef ATOMIC_FETCH_OP |
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#undef ATOMIC_OP_RETURN |
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#undef ATOMIC_OP |
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#ifdef CONFIG_64BIT |
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#define ATOMIC64_INIT(i) { (i) } |
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#define ATOMIC64_OP(op, c_op) \ |
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static __inline__ void atomic64_##op(s64 i, atomic64_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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v->counter c_op i; \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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} |
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#define ATOMIC64_OP_RETURN(op, c_op) \ |
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static __inline__ s64 atomic64_##op##_return(s64 i, atomic64_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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s64 ret; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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ret = (v->counter c_op i); \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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\ |
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return ret; \ |
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} |
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#define ATOMIC64_FETCH_OP(op, c_op) \ |
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static __inline__ s64 atomic64_fetch_##op(s64 i, atomic64_t *v) \ |
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{ \ |
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unsigned long flags; \ |
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s64 ret; \ |
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\ |
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_atomic_spin_lock_irqsave(v, flags); \ |
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ret = v->counter; \ |
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v->counter c_op i; \ |
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_atomic_spin_unlock_irqrestore(v, flags); \ |
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\ |
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return ret; \ |
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} |
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#define ATOMIC64_OPS(op, c_op) \ |
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ATOMIC64_OP(op, c_op) \ |
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ATOMIC64_OP_RETURN(op, c_op) \ |
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ATOMIC64_FETCH_OP(op, c_op) |
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ATOMIC64_OPS(add, +=) |
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ATOMIC64_OPS(sub, -=) |
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#undef ATOMIC64_OPS |
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#define ATOMIC64_OPS(op, c_op) \ |
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ATOMIC64_OP(op, c_op) \ |
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ATOMIC64_FETCH_OP(op, c_op) |
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ATOMIC64_OPS(and, &=) |
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ATOMIC64_OPS(or, |=) |
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ATOMIC64_OPS(xor, ^=) |
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#undef ATOMIC64_OPS |
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#undef ATOMIC64_FETCH_OP |
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#undef ATOMIC64_OP_RETURN |
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#undef ATOMIC64_OP |
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static __inline__ void |
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atomic64_set(atomic64_t *v, s64 i) |
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{ |
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unsigned long flags; |
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_atomic_spin_lock_irqsave(v, flags); |
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v->counter = i; |
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_atomic_spin_unlock_irqrestore(v, flags); |
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} |
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#define atomic64_set_release(v, i) atomic64_set((v), (i)) |
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static __inline__ s64 |
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atomic64_read(const atomic64_t *v) |
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{ |
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return READ_ONCE((v)->counter); |
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} |
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/* exported interface */ |
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#define atomic64_cmpxchg(v, o, n) \ |
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((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n))) |
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new)) |
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#endif /* !CONFIG_64BIT */ |
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#endif /* _ASM_PARISC_ATOMIC_H_ */
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