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239 lines
6.5 KiB
239 lines
6.5 KiB
/* |
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* Neuros Technologies OSD2 board support |
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* |
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* Modified from original 644X-EVM board support. |
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* 2008 (c) Neuros Technology, LLC. |
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* 2009 (c) Jorge Luis Zapata Muga <[email protected]> |
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* 2009 (c) Andrey A. Porodko <[email protected]> |
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* |
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* The Neuros OSD 2.0 is the hardware component of the Neuros Open |
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* Internet Television Platform. Hardware is very close to TI |
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* DM644X-EVM board. It has: |
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* DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC, |
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* USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video. |
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* Additionally realtime clock, IR remote control receiver, |
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* IR Blaster based on MSP430 (firmware although is different |
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* from used in DM644X-EVM), internal ATA-6 3.5” HDD drive |
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* with PATA interface, two muxed red-green leds. |
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* |
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* For more information please refer to |
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* http://wiki.neurostechnology.com/index.php/OSD_2.0_HD |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/gpio.h> |
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#include <linux/leds.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/platform_data/gpio-davinci.h> |
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#include <linux/platform_data/i2c-davinci.h> |
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#include <linux/platform_data/mmc-davinci.h> |
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#include <linux/platform_data/mtd-davinci.h> |
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#include <linux/platform_data/usb-davinci.h> |
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#include <asm/mach-types.h> |
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#include <asm/mach/arch.h> |
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#include <mach/common.h> |
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#include <mach/serial.h> |
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#include <mach/mux.h> |
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#include "davinci.h" |
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#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01" |
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#define LXT971_PHY_ID 0x001378e2 |
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#define LXT971_PHY_MASK 0xfffffff0 |
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#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18 |
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#define NTOSD2_MSP430_I2C_ADDR 0x59 |
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#define NTOSD2_MSP430_IRQ 2 |
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/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA, |
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* 2048 blocks in the device, 64 pages per block, 2048 bytes per |
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* page. |
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*/ |
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#define NAND_BLOCK_SIZE SZ_128K |
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static struct mtd_partition davinci_ntosd2_nandflash_partition[] = { |
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{ |
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/* UBL (a few copies) plus U-Boot */ |
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.name = "bootloader", |
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.offset = 0, |
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.size = 15 * NAND_BLOCK_SIZE, |
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.mask_flags = MTD_WRITEABLE, /* force read-only */ |
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}, { |
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/* U-Boot environment */ |
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.name = "params", |
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.offset = MTDPART_OFS_APPEND, |
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.size = 1 * NAND_BLOCK_SIZE, |
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.mask_flags = 0, |
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}, { |
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/* Kernel */ |
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.name = "kernel", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_4M, |
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.mask_flags = 0, |
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}, { |
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/* File System */ |
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.name = "filesystem", |
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.offset = MTDPART_OFS_APPEND, |
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.size = MTDPART_SIZ_FULL, |
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.mask_flags = 0, |
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} |
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/* A few blocks at end hold a flash Bad Block Table. */ |
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}; |
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static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = { |
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.core_chipsel = 0, |
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.parts = davinci_ntosd2_nandflash_partition, |
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.nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition), |
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.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, |
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.ecc_bits = 1, |
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.bbt_options = NAND_BBT_USE_FLASH, |
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}; |
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static struct resource davinci_ntosd2_nandflash_resource[] = { |
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{ |
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.start = DM644X_ASYNC_EMIF_DATA_CE0_BASE, |
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.end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.start = DM644X_ASYNC_EMIF_CONTROL_BASE, |
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.end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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static struct platform_device davinci_ntosd2_nandflash_device = { |
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.name = "davinci_nand", |
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.id = 0, |
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.dev = { |
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.platform_data = &davinci_ntosd2_nandflash_data, |
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}, |
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.num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource), |
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.resource = davinci_ntosd2_nandflash_resource, |
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}; |
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static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); |
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static struct platform_device davinci_fb_device = { |
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.name = "davincifb", |
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.id = -1, |
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.dev = { |
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.dma_mask = &davinci_fb_dma_mask, |
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.coherent_dma_mask = DMA_BIT_MASK(32), |
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}, |
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.num_resources = 0, |
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}; |
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static const struct gpio_led ntosd2_leds[] = { |
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{ .name = "led1_green", .gpio = 10, }, |
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{ .name = "led1_red", .gpio = 11, }, |
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{ .name = "led2_green", .gpio = 12, }, |
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{ .name = "led2_red", .gpio = 13, }, |
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}; |
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static struct gpio_led_platform_data ntosd2_leds_data = { |
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.num_leds = ARRAY_SIZE(ntosd2_leds), |
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.leds = ntosd2_leds, |
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}; |
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static struct platform_device ntosd2_leds_dev = { |
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.name = "leds-gpio", |
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.id = -1, |
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.dev = { |
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.platform_data = &ntosd2_leds_data, |
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}, |
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}; |
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static struct platform_device *davinci_ntosd2_devices[] __initdata = { |
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&davinci_fb_device, |
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&ntosd2_leds_dev, |
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}; |
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static void __init davinci_ntosd2_map_io(void) |
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{ |
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dm644x_init(); |
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} |
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static struct davinci_mmc_config davinci_ntosd2_mmc_config = { |
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.wires = 4, |
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}; |
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#define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ |
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IS_ENABLED(CONFIG_PATA_BK3710)) |
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#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI) |
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static __init void davinci_ntosd2_init(void) |
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{ |
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int ret; |
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struct clk *aemif_clk; |
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struct davinci_soc_info *soc_info = &davinci_soc_info; |
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dm644x_register_clocks(); |
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dm644x_init_devices(); |
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ret = dm644x_gpio_register(); |
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if (ret) |
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pr_warn("%s: GPIO init failed: %d\n", __func__, ret); |
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aemif_clk = clk_get(NULL, "aemif"); |
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clk_prepare_enable(aemif_clk); |
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if (HAS_ATA) { |
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if (HAS_NAND) |
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pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n" |
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"\tDisable IDE for NAND/NOR support\n"); |
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davinci_init_ide(); |
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} else if (HAS_NAND) { |
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davinci_cfg_reg(DM644X_HPIEN_DISABLE); |
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davinci_cfg_reg(DM644X_ATAEN_DISABLE); |
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/* only one device will be jumpered and detected */ |
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if (HAS_NAND) |
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platform_device_register( |
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&davinci_ntosd2_nandflash_device); |
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} |
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platform_add_devices(davinci_ntosd2_devices, |
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ARRAY_SIZE(davinci_ntosd2_devices)); |
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davinci_serial_init(dm644x_serial_device); |
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dm644x_init_asp(); |
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soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; |
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davinci_setup_usb(1000, 8); |
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/* |
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* Mux the pins to be GPIOs, VLYNQEN is already done at startup. |
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* The AEAWx are five new AEAW pins that can be muxed by separately. |
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* They are a bitmask for GPIO management. According TI |
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* documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ |
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* gpio(10,11,12,13) for leds any combination of bits works except |
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* four last. So we are to reset all five. |
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*/ |
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davinci_cfg_reg(DM644X_AEAW0); |
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davinci_cfg_reg(DM644X_AEAW1); |
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davinci_cfg_reg(DM644X_AEAW2); |
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davinci_cfg_reg(DM644X_AEAW3); |
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davinci_cfg_reg(DM644X_AEAW4); |
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davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); |
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} |
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MACHINE_START(NEUROS_OSD2, "Neuros OSD2") |
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/* Maintainer: Neuros Technologies <[email protected]> */ |
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.atag_offset = 0x100, |
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.map_io = davinci_ntosd2_map_io, |
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.init_irq = dm644x_init_irq, |
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.init_time = dm644x_init_time, |
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.init_machine = davinci_ntosd2_init, |
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.init_late = davinci_init_late, |
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.dma_zone_size = SZ_128M, |
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MACHINE_END
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