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28 lines
972 B
28 lines
972 B
NVIDIA Tegra30 timer |
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The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free |
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running counter, and 5 watchdog modules. The first two channels may also |
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trigger a legacy watchdog reset. |
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Required properties: |
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- compatible : For Tegra30, must contain "nvidia,tegra30-timer". Otherwise, |
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must contain '"nvidia,<chip>-timer", "nvidia,tegra30-timer"' where |
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<chip> is tegra124 or tegra132. |
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- reg : Specifies base physical address and size of the registers. |
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- interrupts : A list of 6 interrupts; one per each of timer channels 1 |
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through 5, and one for the shared interrupt for the remaining channels. |
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- clocks : Must contain one entry, for the module clock. |
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See ../clocks/clock-bindings.txt for details. |
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timer { |
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compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; |
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reg = <0x60005000 0x400>; |
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interrupts = <0 0 0x04 |
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0 1 0x04 |
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0 41 0x04 |
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0 42 0x04 |
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0 121 0x04 |
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0 122 0x04>; |
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clocks = <&tegra_car 214>; |
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};
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