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288 lines
7.7 KiB
288 lines
7.7 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/sram/sram.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Generic on-chip SRAM |
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maintainers: |
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- Rob Herring <[email protected]> |
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description: |+ |
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Simple IO memory regions to be managed by the genalloc API. |
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Each child of the sram node specifies a region of reserved memory. Each |
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child node should use a 'reg' property to specify a specific range of |
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reserved memory. |
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Following the generic-names recommended practice, node names should |
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reflect the purpose of the node. Unit address (@<address>) should be |
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appended to the name. |
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properties: |
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$nodename: |
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pattern: "^sram(@.*)?" |
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compatible: |
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contains: |
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enum: |
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- mmio-sram |
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- atmel,sama5d2-securam |
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- rockchip,rk3288-pmu-sram |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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description: |
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A list of phandle and clock specifier pair that controls the single |
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SRAM clock. |
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"#address-cells": |
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const: 1 |
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"#size-cells": |
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const: 1 |
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ranges: |
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maxItems: 1 |
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description: |
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Should translate from local addresses within the sram to bus addresses. |
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no-memory-wc: |
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description: |
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The flag indicating, that SRAM memory region has not to be remapped |
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as write combining. WC is used by default. |
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type: boolean |
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patternProperties: |
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"^([a-z]*-)?sram(-section)?@[a-f0-9]+$": |
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type: object |
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description: |
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Each child of the sram node specifies a region of reserved memory. |
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properties: |
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compatible: |
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description: |
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Should contain a vendor specific string in the form |
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<vendor>,[<device>-]<usage> |
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contains: |
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enum: |
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- allwinner,sun4i-a10-sram-a3-a4 |
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- allwinner,sun4i-a10-sram-c1 |
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- allwinner,sun4i-a10-sram-d |
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- allwinner,sun9i-a80-smp-sram |
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- allwinner,sun50i-a64-sram-c |
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- amlogic,meson8-ao-arc-sram |
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- amlogic,meson8b-ao-arc-sram |
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- amlogic,meson8-smp-sram |
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- amlogic,meson8b-smp-sram |
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- amlogic,meson-gxbb-scp-shmem |
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- amlogic,meson-axg-scp-shmem |
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- renesas,smp-sram |
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- rockchip,rk3066-smp-sram |
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- samsung,exynos4210-sysram |
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- samsung,exynos4210-sysram-ns |
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- socionext,milbeaut-smp-sram |
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reg: |
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description: |
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IO mem address range, relative to the SRAM range. |
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maxItems: 1 |
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pool: |
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description: |
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Indicates that the particular reserved SRAM area is addressable |
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and in use by another device or devices. |
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type: boolean |
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export: |
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description: |
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Indicates that the reserved SRAM area may be accessed outside |
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of the kernel, e.g. by bootloader or userspace. |
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type: boolean |
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protect-exec: |
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description: | |
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Same as 'pool' above but with the additional constraint that code |
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will be run from the region and that the memory is maintained as |
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read-only, executable during code execution. NOTE: This region must |
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be page aligned on start and end in order to properly allow |
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manipulation of the page attributes. |
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type: boolean |
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label: |
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description: |
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The name for the reserved partition, if omitted, the label is taken |
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from the node name excluding the unit address. |
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required: |
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- reg |
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additionalProperties: false |
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required: |
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- compatible |
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- reg |
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if: |
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properties: |
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compatible: |
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contains: |
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const: rockchip,rk3288-pmu-sram |
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else: |
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required: |
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- "#address-cells" |
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- "#size-cells" |
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- ranges |
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additionalProperties: false |
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examples: |
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- | |
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sram@5c000000 { |
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compatible = "mmio-sram"; |
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reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x5c000000 0x40000>; |
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smp-sram@100 { |
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reg = <0x100 0x50>; |
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}; |
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device-sram@1000 { |
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reg = <0x1000 0x1000>; |
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pool; |
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}; |
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exported-sram@20000 { |
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reg = <0x20000 0x20000>; |
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export; |
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}; |
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}; |
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- | |
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// Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup |
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// of the secondary cores. Once the core gets powered up it executes the |
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// code that is residing at some specific location of the SYSRAM. |
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// |
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// Therefore reserved section sub-nodes have to be added to the mmio-sram |
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// declaration. These nodes are of two types depending upon secure or |
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// non-secure execution environment. |
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sram@2020000 { |
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compatible = "mmio-sram"; |
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reg = <0x02020000 0x54000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x02020000 0x54000>; |
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smp-sram@0 { |
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compatible = "samsung,exynos4210-sysram"; |
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reg = <0x0 0x1000>; |
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}; |
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smp-sram@53000 { |
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compatible = "samsung,exynos4210-sysram-ns"; |
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reg = <0x53000 0x1000>; |
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}; |
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}; |
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- | |
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// Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores. |
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// Once the core gets powered up it executes the code that is residing at a |
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// specific location. |
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// |
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// Therefore a reserved section sub-node has to be added to the mmio-sram |
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// declaration. |
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sram@d9000000 { |
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compatible = "mmio-sram"; |
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reg = <0xd9000000 0x20000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0xd9000000 0x20000>; |
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smp-sram@1ff80 { |
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compatible = "amlogic,meson8b-smp-sram"; |
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reg = <0x1ff80 0x8>; |
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}; |
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}; |
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- | |
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sram@e63c0000 { |
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compatible = "mmio-sram"; |
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reg = <0xe63c0000 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0xe63c0000 0x1000>; |
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smp-sram@0 { |
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compatible = "renesas,smp-sram"; |
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reg = <0 0x10>; |
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}; |
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}; |
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- | |
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sram@10080000 { |
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compatible = "mmio-sram"; |
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reg = <0x10080000 0x10000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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smp-sram@10080000 { |
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compatible = "rockchip,rk3066-smp-sram"; |
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reg = <0x10080000 0x50>; |
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}; |
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}; |
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- | |
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// Rockchip's rk3288 SoC uses the sram of pmu to store the function of |
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// resume from maskrom(the 1st level loader). This is a common use of |
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// the "pmu-sram" because it keeps power even in low power states |
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// in the system. |
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sram@ff720000 { |
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compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; |
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reg = <0xff720000 0x1000>; |
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}; |
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- | |
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// Allwinner's A80 SoC uses part of the secure sram for hotplugging of the |
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// primary core (cpu0). Once the core gets powered up it checks if a magic |
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// value is set at a specific location. If it is then the BROM will jump |
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// to the software entry address, instead of executing a standard boot. |
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// |
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// Also there are no "secure-only" properties. The implementation should |
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// check if this SRAM is usable first. |
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sram@20000 { |
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// 256 KiB secure SRAM at 0x20000 |
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compatible = "mmio-sram"; |
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reg = <0x00020000 0x40000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x00020000 0x40000>; |
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smp-sram@1000 { |
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// This is checked by BROM to determine if |
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// cpu0 should jump to SMP entry vector |
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compatible = "allwinner,sun9i-a80-smp-sram"; |
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reg = <0x1000 0x8>; |
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}; |
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}; |
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- | |
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sram@0 { |
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compatible = "mmio-sram"; |
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reg = <0x0 0x10000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x0 0x10000>; |
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smp-sram@f100 { |
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compatible = "socionext,milbeaut-smp-sram"; |
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reg = <0xf100 0x20>; |
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}; |
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};
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