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103 lines
3.1 KiB
103 lines
3.1 KiB
Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) |
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The QUP core is an AHB slave that provides a common data path (an output FIFO |
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and an input FIFO) for serial peripheral interface (SPI) mini-core. |
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SPI in master mode supports up to 50MHz, up to four chip selects, programmable |
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data path from 4 bits to 32 bits and numerous protocol variants. |
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Required properties: |
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- compatible: Should contain: |
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"qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064. |
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"qcom,spi-qup-v2.1.1" for 8974 and later |
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"qcom,spi-qup-v2.2.1" for 8974 v2 and later. |
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- reg: Should contain base register location and length |
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- interrupts: Interrupt number used by this controller |
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- clocks: Should contain the core clock and the AHB clock. |
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- clock-names: Should be "core" for the core clock and "iface" for the |
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AHB clock. |
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- #address-cells: Number of cells required to define a chip select |
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address on the SPI bus. Should be set to 1. |
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- #size-cells: Should be zero. |
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Optional properties: |
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- spi-max-frequency: Specifies maximum SPI clock frequency, |
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Units - Hz. Definition as per |
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Documentation/devicetree/bindings/spi/spi-bus.txt |
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- num-cs: total number of chipselects |
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- cs-gpios: should specify GPIOs used for chipselects. |
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The gpios will be referred to as reg = <index> in the SPI child |
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nodes. If unspecified, a single SPI device without a chip |
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select can be used. |
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- dmas: Two DMA channel specifiers following the convention outlined |
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in bindings/dma/dma.txt |
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- dma-names: Names for the dma channels, if present. There must be at |
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least one channel named "tx" for transmit and named "rx" for |
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receive. |
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SPI slave nodes must be children of the SPI master node and can contain |
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properties described in Documentation/devicetree/bindings/spi/spi-bus.txt |
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Example: |
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spi_8: spi@f9964000 { /* BLSP2 QUP2 */ |
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compatible = "qcom,spi-qup-v2"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xf9964000 0x1000>; |
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interrupts = <0 102 0>; |
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spi-max-frequency = <19200000>; |
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clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; |
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clock-names = "core", "iface"; |
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dmas = <&blsp1_bam 13>, <&blsp1_bam 12>; |
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dma-names = "rx", "tx"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi8_default>; |
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device@0 { |
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compatible = "arm,pl022-dummy"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0>; /* Chip select 0 */ |
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spi-max-frequency = <19200000>; |
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spi-cpol; |
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}; |
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device@1 { |
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compatible = "arm,pl022-dummy"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <1>; /* Chip select 1 */ |
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spi-max-frequency = <9600000>; |
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spi-cpha; |
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}; |
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device@2 { |
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compatible = "arm,pl022-dummy"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <2>; /* Chip select 2 */ |
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spi-max-frequency = <19200000>; |
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spi-cpol; |
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spi-cpha; |
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}; |
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device@3 { |
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compatible = "arm,pl022-dummy"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <3>; /* Chip select 3 */ |
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spi-max-frequency = <19200000>; |
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spi-cpol; |
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spi-cpha; |
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spi-cs-high; |
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}; |
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};
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