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47 lines
1.5 KiB
47 lines
1.5 KiB
* Nuvoton FLASH Interface Unit (FIU) SPI Controller |
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NPCM FIU supports single, dual and quad communication interface. |
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The NPCM7XX supports three FIU modules, |
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FIU0 and FIUx supports two chip selects, |
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FIU3 support four chip select. |
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Required properties: |
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- compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC |
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- #address-cells : should be 1. |
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- #size-cells : should be 0. |
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- reg : the first contains the register location and length, |
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the second contains the memory mapping address and length |
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- reg-names: Should contain the reg names "control" and "memory" |
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- clocks : phandle of FIU reference clock. |
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Required properties in case the pins can be muxed: |
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- pinctrl-names : a pinctrl state named "default" must be defined. |
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- pinctrl-0 : phandle referencing pin configuration of the device. |
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Optional property: |
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- nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. |
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Aliases: |
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- All the FIU controller nodes should be represented in the aliases node using |
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the following format 'fiu{n}' where n is a unique number for the alias. |
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In the NPCM7XX BMC: |
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fiu0 represent fiu 0 controller |
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fiu1 represent fiu 3 controller |
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fiu2 represent fiu x controller |
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Example: |
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fiu3: spi@c00000000 { |
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compatible = "nuvoton,npcm750-fiu"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; |
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reg-names = "control", "memory"; |
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clocks = <&clk NPCM7XX_CLK_AHB>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&spi3_pins>; |
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spi-nor@0 { |
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... |
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}; |
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}; |
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