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245 lines
7.0 KiB
245 lines
7.0 KiB
Broadcom SPI controller |
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The Broadcom SPI controller is a SPI master found on various SOCs, including |
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BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits |
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of : |
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MSPI : SPI master controller can read and write to a SPI slave device |
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BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration |
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for flash reads and be configured to do single, double, quad lane |
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io with 3-byte and 4-byte addressing support. |
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Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP. |
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MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance |
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of a MSPI master without the BSPI to use with non flash slave devices that |
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use SPI protocol. |
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Required properties: |
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- #address-cells: |
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Must be <1>, as required by generic SPI binding. |
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- #size-cells: |
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Must be <0>, also as required by generic SPI binding. |
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- compatible: |
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Must be one of : |
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"brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs |
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"brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7445-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI |
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BRCMSTB SoCs |
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"brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on Cygnus, NSP |
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"brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi" : NS2 SoCs |
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- reg: |
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Define the bases and ranges of the associated I/O address spaces. |
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The required range is MSPI controller registers. |
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- reg-names: |
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First name does not matter, but must be reserved for the MSPI controller |
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register range as mentioned in 'reg' above, and will typically contain |
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- "bspi_regs": BSPI register range, not required with compatible |
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"spi-brcmstb-mspi" |
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- "mspi_regs": MSPI register range is required for compatible strings |
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- "intr_regs", "intr_status_reg" : Interrupt and status register for |
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NSP, NS2, Cygnus SoC |
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- interrupts |
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The interrupts used by the MSPI and/or BSPI controller. |
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- interrupt-names: |
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Names of interrupts associated with MSPI |
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- "mspi_halted" : |
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- "mspi_done": Indicates that the requested SPI operation is complete. |
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- "spi_lr_fullness_reached" : Linear read BSPI pipe full |
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- "spi_lr_session_aborted" : Linear read BSPI pipe aborted |
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- "spi_lr_impatient" : Linear read BSPI requested when pipe empty |
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- "spi_lr_session_done" : Linear read BSPI session done |
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- clocks: |
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A phandle to the reference clock for this block. |
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Optional properties: |
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- native-endian |
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Defined when using BE SoC and device uses BE register read/write |
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Recommended optional m25p80 properties: |
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- spi-rx-bus-width: Definition as per |
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Documentation/devicetree/bindings/spi/spi-bus.txt |
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Examples: |
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BRCMSTB SoC Example: |
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SPI Master (MSPI+BSPI) for SPI-NOR access: |
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spi@f03e3400 { |
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#address-cells = <0x1>; |
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#size-cells = <0x0>; |
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compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi"; |
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reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>; |
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reg-names = "cs_reg", "mspi", "bspi"; |
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interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>; |
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interrupt-parent = <0x1c>; |
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interrupt-names = "mspi_halted", |
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"mspi_done", |
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"spi_lr_overread", |
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"spi_lr_session_done", |
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"spi_lr_impatient", |
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"spi_lr_session_aborted", |
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"spi_lr_fullness_reached"; |
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clocks = <&hif_spi>; |
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clock-names = "sw_spi"; |
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m25p80@0 { |
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#size-cells = <0x2>; |
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#address-cells = <0x2>; |
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compatible = "m25p80"; |
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reg = <0x0>; |
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spi-max-frequency = <0x2625a00>; |
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spi-cpol; |
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spi-cpha; |
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m25p,fast-read; |
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flash0.bolt@0 { |
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reg = <0x0 0x0 0x0 0x100000>; |
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}; |
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flash0.macadr@100000 { |
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reg = <0x0 0x100000 0x0 0x10000>; |
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}; |
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flash0.nvram@110000 { |
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reg = <0x0 0x110000 0x0 0x10000>; |
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}; |
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flash0.kernel@120000 { |
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reg = <0x0 0x120000 0x0 0x400000>; |
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}; |
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flash0.devtree@520000 { |
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reg = <0x0 0x520000 0x0 0x10000>; |
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}; |
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flash0.splash@530000 { |
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reg = <0x0 0x530000 0x0 0x80000>; |
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}; |
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flash0@0 { |
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reg = <0x0 0x0 0x0 0x4000000>; |
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}; |
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}; |
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}; |
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MSPI master for any SPI device : |
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spi@f0416000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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clocks = <&upg_fixed>; |
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compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi"; |
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reg = <0xf0416000 0x180>; |
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reg-names = "mspi"; |
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interrupts = <0x14>; |
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interrupt-parent = <&irq0_aon_intc>; |
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interrupt-names = "mspi_done"; |
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}; |
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iProc SoC Example: |
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qspi: spi@18027200 { |
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compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; |
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reg = <0x18027200 0x184>, |
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<0x18027000 0x124>, |
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<0x1811c408 0x004>, |
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<0x180273a0 0x01c>; |
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reg-names = "mspi_regs", "bspi_regs", "intr_regs", "intr_status_reg"; |
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = |
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"spi_lr_fullness_reached", |
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"spi_lr_session_aborted", |
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"spi_lr_impatient", |
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"spi_lr_session_done", |
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"mspi_done", |
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"mspi_halted"; |
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clocks = <&iprocmed>; |
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clock-names = "iprocmed"; |
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num-cs = <2>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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NS2 SoC Example: |
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qspi: spi@66470200 { |
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compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"; |
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reg = <0x66470200 0x184>, |
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<0x66470000 0x124>, |
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<0x67017408 0x004>, |
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<0x664703a0 0x01c>; |
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reg-names = "mspi", "bspi", "intr_regs", |
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"intr_status_reg"; |
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interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "spi_l1_intr"; |
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clocks = <&iprocmed>; |
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clock-names = "iprocmed"; |
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num-cs = <2>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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m25p80 node for NSP, NS2 |
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&qspi { |
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flash: m25p80@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "m25p80"; |
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reg = <0x0>; |
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spi-max-frequency = <12500000>; |
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m25p,fast-read; |
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spi-cpol; |
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spi-cpha; |
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partition@0 { |
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label = "boot"; |
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reg = <0x00000000 0x000a0000>; |
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}; |
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partition@a0000 { |
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label = "env"; |
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reg = <0x000a0000 0x00060000>; |
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}; |
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partition@100000 { |
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label = "system"; |
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reg = <0x00100000 0x00600000>; |
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}; |
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partition@700000 { |
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label = "rootfs"; |
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reg = <0x00700000 0x01900000>; |
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}; |
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};
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