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515 lines
15 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/soc/ti/ti,pruss.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: |+ |
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TI Programmable Real-Time Unit and Industrial Communication Subsystem |
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maintainers: |
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- Suman Anna <[email protected]> |
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description: |+ |
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The Programmable Real-Time Unit and Industrial Communication Subsystem |
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(PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, |
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Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC |
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cores (Programmable Real-Time Units, or PRUs), shared RAM, data and |
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instruction RAMs, some internal peripheral modules to facilitate industrial |
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communication, and an interrupt controller. |
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The programmable nature of the PRUs provide flexibility to implement custom |
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peripheral interfaces, fast real-time responses, or specialized data handling. |
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The common peripheral modules include the following, |
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- an Ethernet MII_RT module with two MII ports |
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- an MDIO port to control external Ethernet PHYs |
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- an Industrial Ethernet Peripheral (IEP) to manage/generate Industrial |
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Ethernet functions |
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- an Enhanced Capture Module (eCAP) |
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- an Industrial Ethernet Timer with 7/9 capture and 16 compare events |
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- a 16550-compatible UART to support PROFIBUS |
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- Enhanced GPIO with async capture and serial support |
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A PRU-ICSS subsystem can have up to three shared data memories. A PRU core |
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acts on a primary Data RAM (there are usually 2 Data RAMs) at its address |
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0x0, but also has access to a secondary Data RAM (primary to the other PRU |
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core) at its address 0x2000. A shared Data RAM, if present, can be accessed |
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by both the PRU cores. The Interrupt Controller (INTC) and a CFG module are |
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common to both the PRU cores. Each PRU core also has a private instruction |
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RAM, and specific register spaces for Control and Debug functionalities. |
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Various sub-modules within a PRU-ICSS subsystem are represented as individual |
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nodes and are defined using a parent-child hierarchy depending on their |
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integration within the IP and the SoC. These nodes are described in the |
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following sections. |
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PRU-ICSS Node |
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============== |
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Each PRU-ICSS instance is represented as its own node with the individual PRU |
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processor cores, the memories node, an INTC node and an MDIO node represented |
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as child nodes within this PRUSS node. This node shall be a child of the |
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corresponding interconnect bus nodes or target-module nodes. |
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See ../../mfd/syscon.yaml for generic SysCon binding details. |
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properties: |
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$nodename: |
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pattern: "^(pruss|icssg)@[0-9a-f]+$" |
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compatible: |
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enum: |
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- ti,am3356-pruss # for AM335x SoC family |
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- ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0 |
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- ti,am4376-pruss1 # for AM437x SoC family and PRUSS unit 1 |
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- ti,am5728-pruss # for AM57xx SoC family |
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- ti,k2g-pruss # for 66AK2G SoC family |
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- ti,am654-icssg # for K3 AM65x SoC family |
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- ti,j721e-icssg # for K3 J721E SoC family |
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reg: |
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maxItems: 1 |
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"#address-cells": |
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const: 1 |
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"#size-cells": |
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const: 1 |
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ranges: |
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maxItems: 1 |
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dma-ranges: |
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maxItems: 1 |
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power-domains: |
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description: | |
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This property is as per sci-pm-domain.txt. |
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patternProperties: |
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memories@[a-f0-9]+$: |
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description: | |
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The various Data RAMs within a single PRU-ICSS unit are represented as a |
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single node with the name 'memories'. |
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type: object |
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properties: |
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reg: |
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minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM. |
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maxItems: 3 |
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items: |
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- description: Address and size of the Data RAM0. |
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- description: Address and size of the Data RAM1. |
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- description: | |
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Address and size of the Shared Data RAM. Note that on AM437x one |
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of two PRUSS units don't contain Shared RAM, while the second one |
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has it. |
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reg-names: |
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minItems: 2 |
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maxItems: 3 |
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items: |
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- const: dram0 |
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- const: dram1 |
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- const: shrdram2 |
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required: |
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- reg |
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- reg-names |
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additionalProperties: false |
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cfg@[a-f0-9]+$: |
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description: | |
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PRU-ICSS configuration space. CFG sub-module represented as a SysCon. |
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type: object |
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properties: |
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compatible: |
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items: |
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- const: ti,pruss-cfg |
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- const: syscon |
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"#address-cells": |
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const: 1 |
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"#size-cells": |
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const: 1 |
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reg: |
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maxItems: 1 |
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ranges: |
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maxItems: 1 |
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clocks: |
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type: object |
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properties: |
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"#address-cells": |
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const: 1 |
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"#size-cells": |
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const: 0 |
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patternProperties: |
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coreclk-mux@[a-f0-9]+$: |
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description: | |
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This is applicable only for ICSSG (K3 SoCs). The ICSSG modules |
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core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or |
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ICSSG_ICLK. This node models this clock mux and should have the |
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name "coreclk-mux". |
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type: object |
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properties: |
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'#clock-cells': |
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const: 0 |
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clocks: |
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items: |
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- description: ICSSG_CORE Clock |
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- description: ICSSG_ICLK Clock |
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assigned-clocks: |
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maxItems: 1 |
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assigned-clock-parents: |
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maxItems: 1 |
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description: | |
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Standard assigned-clocks-parents definition used for selecting |
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mux parent (one of the mux input). |
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reg: |
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maxItems: 1 |
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required: |
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- clocks |
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additionalProperties: false |
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iepclk-mux@[a-f0-9]+$: |
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description: | |
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The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or |
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CORE_CLK (OCP_CLK in older SoCs). This node models this clock |
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mux and should have the name "iepclk-mux". |
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type: object |
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properties: |
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'#clock-cells': |
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const: 0 |
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clocks: |
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items: |
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- description: ICSSG_IEP Clock |
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- description: Core Clock (OCP Clock in older SoCs) |
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assigned-clocks: |
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maxItems: 1 |
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assigned-clock-parents: |
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maxItems: 1 |
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description: | |
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Standard assigned-clocks-parents definition used for selecting |
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mux parent (one of the mux input). |
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reg: |
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maxItems: 1 |
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required: |
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- clocks |
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additionalProperties: false |
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additionalProperties: false |
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iep@[a-f0-9]+$: |
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description: | |
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Industrial Ethernet Peripheral to manage/generate Industrial Ethernet |
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functions such as time stamping. Each PRUSS has either 1 IEP (on AM335x, |
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AM437x, AM57xx & 66AK2G SoCs) or 2 IEPs (on K3 AM65x & J721E SoCs ). IEP |
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is used for creating PTP clocks and generating PPS signals. |
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type: object |
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mii-rt@[a-f0-9]+$: |
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description: | |
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Real-Time Ethernet to support multiple industrial communication protocols. |
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MII-RT sub-module represented as a SysCon. |
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type: object |
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properties: |
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compatible: |
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items: |
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- const: ti,pruss-mii |
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- const: syscon |
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reg: |
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maxItems: 1 |
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additionalProperties: false |
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mii-g-rt@[a-f0-9]+$: |
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description: | |
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The Real-time Media Independent Interface to support multiple industrial |
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communication protocols (G stands for Gigabit). MII-G-RT sub-module |
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represented as a SysCon. |
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type: object |
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properties: |
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compatible: |
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items: |
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- const: ti,pruss-mii-g |
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- const: syscon |
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reg: |
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maxItems: 1 |
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additionalProperties: false |
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interrupt-controller@[a-f0-9]+$: |
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description: | |
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PRUSS INTC Node. Each PRUSS has a single interrupt controller instance |
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that is common to all the PRU cores. This should be represented as an |
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interrupt-controller node. |
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allOf: |
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- $ref: /schemas/interrupt-controller/ti,pruss-intc.yaml# |
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type: object |
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mdio@[a-f0-9]+$: |
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description: | |
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MDIO Node. Each PRUSS has an MDIO module that can be used to control |
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external PHYs. The MDIO module used within the PRU-ICSS is an instance of |
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the MDIO Controller used in TI Davinci SoCs. |
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allOf: |
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- $ref: /schemas/net/ti,davinci-mdio.yaml# |
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type: object |
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"^(pru|rtu|txpru)@[0-9a-f]+$": |
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description: | |
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PRU Node. Each PRUSS has dual PRU cores, each represented as a RemoteProc |
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device through a PRU child node each. Each node can optionally be rendered |
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inactive by using the standard DT string property, "status". The ICSSG IP |
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present on K3 SoCs have additional auxiliary PRU cores with slightly |
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different IP integration. |
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allOf: |
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- $ref: /schemas/remoteproc/ti,pru-rproc.yaml# |
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type: object |
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required: |
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- compatible |
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- reg |
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- ranges |
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additionalProperties: false |
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# Due to inability of correctly verifying sub-nodes with an @address through |
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# the "required" list, the required sub-nodes below are commented out for now. |
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#required: |
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# - memories |
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# - interrupt-controller |
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# - pru |
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if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- ti,k2g-pruss |
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- ti,am654-icssg |
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- ti,j721e-icssg |
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then: |
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required: |
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- power-domains |
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examples: |
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- | |
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/* Example 1 AM33xx PRU-ICSS */ |
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pruss: pruss@0 { |
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compatible = "ti,am3356-pruss"; |
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reg = <0x0 0x80000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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pruss_mem: memories@0 { |
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reg = <0x0 0x2000>, |
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<0x2000 0x2000>, |
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<0x10000 0x3000>; |
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reg-names = "dram0", "dram1", "shrdram2"; |
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}; |
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pruss_cfg: cfg@26000 { |
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compatible = "ti,pruss-cfg", "syscon"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x26000 0x2000>; |
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ranges = <0x00 0x26000 0x2000>; |
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clocks { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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pruss_iepclk_mux: iepclk-mux@30 { |
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reg = <0x30>; |
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#clock-cells = <0>; |
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clocks = <&l3_gclk>, /* icss_iep */ |
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<&pruss_ocp_gclk>; /* icss_ocp */ |
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}; |
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}; |
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}; |
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pruss_mii_rt: mii-rt@32000 { |
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compatible = "ti,pruss-mii", "syscon"; |
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reg = <0x32000 0x58>; |
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}; |
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pruss_intc: interrupt-controller@20000 { |
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compatible = "ti,pruss-intc"; |
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reg = <0x20000 0x2000>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupts = <20 21 22 23 24 25 26 27>; |
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interrupt-names = "host_intr0", "host_intr1", |
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"host_intr2", "host_intr3", |
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"host_intr4", "host_intr5", |
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"host_intr6", "host_intr7"; |
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}; |
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pru0: pru@34000 { |
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compatible = "ti,am3356-pru"; |
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reg = <0x34000 0x2000>, |
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<0x22000 0x400>, |
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<0x22400 0x100>; |
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reg-names = "iram", "control", "debug"; |
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firmware-name = "am335x-pru0-fw"; |
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}; |
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pru1: pru@38000 { |
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compatible = "ti,am3356-pru"; |
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reg = <0x38000 0x2000>, |
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<0x24000 0x400>, |
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<0x24400 0x100>; |
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reg-names = "iram", "control", "debug"; |
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firmware-name = "am335x-pru1-fw"; |
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}; |
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pruss_mdio: mdio@32400 { |
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compatible = "ti,davinci_mdio"; |
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reg = <0x32400 0x90>; |
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clocks = <&dpll_core_m4_ck>; |
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clock-names = "fck"; |
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bus_freq = <1000000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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- | |
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/* Example 2 AM43xx PRU-ICSS with PRUSS1 node */ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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pruss1: pruss@0 { |
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compatible = "ti,am4376-pruss1"; |
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reg = <0x0 0x40000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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pruss1_mem: memories@0 { |
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reg = <0x0 0x2000>, |
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<0x2000 0x2000>, |
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<0x10000 0x8000>; |
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reg-names = "dram0", "dram1", "shrdram2"; |
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}; |
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pruss1_cfg: cfg@26000 { |
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compatible = "ti,pruss-cfg", "syscon"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x26000 0x2000>; |
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ranges = <0x00 0x26000 0x2000>; |
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clocks { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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pruss1_iepclk_mux: iepclk-mux@30 { |
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reg = <0x30>; |
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#clock-cells = <0>; |
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clocks = <&sysclk_div>, /* icss_iep */ |
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<&pruss_ocp_gclk>; /* icss_ocp */ |
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}; |
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}; |
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}; |
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pruss1_mii_rt: mii-rt@32000 { |
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compatible = "ti,pruss-mii", "syscon"; |
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reg = <0x32000 0x58>; |
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}; |
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pruss1_intc: interrupt-controller@20000 { |
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compatible = "ti,pruss-intc"; |
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reg = <0x20000 0x2000>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "host_intr0", "host_intr1", |
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"host_intr2", "host_intr3", |
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"host_intr4", |
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"host_intr6", "host_intr7"; |
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ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ |
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}; |
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pru1_0: pru@34000 { |
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compatible = "ti,am4376-pru"; |
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reg = <0x34000 0x3000>, |
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<0x22000 0x400>, |
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<0x22400 0x100>; |
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reg-names = "iram", "control", "debug"; |
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firmware-name = "am437x-pru1_0-fw"; |
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}; |
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pru1_1: pru@38000 { |
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compatible = "ti,am4376-pru"; |
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reg = <0x38000 0x3000>, |
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<0x24000 0x400>, |
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<0x24400 0x100>; |
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reg-names = "iram", "control", "debug"; |
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firmware-name = "am437x-pru1_1-fw"; |
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}; |
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pruss1_mdio: mdio@32400 { |
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compatible = "ti,davinci_mdio"; |
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reg = <0x32400 0x90>; |
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clocks = <&dpll_core_m4_ck>; |
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clock-names = "fck"; |
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bus_freq = <1000000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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...
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