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78 lines
2.4 KiB
78 lines
2.4 KiB
MPC5121 PSC Device Tree Bindings |
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PSC in UART mode |
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---------------- |
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For PSC in UART mode the needed PSC serial devices |
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are specified by fsl,mpc5121-psc-uart nodes in the |
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fsl,mpc5121-immr SoC node. Additionally the PSC FIFO |
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Controller node fsl,mpc5121-psc-fifo is required there: |
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fsl,mpc512x-psc-uart nodes |
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-------------------------- |
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Required properties : |
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- compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc" |
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Supported <soc>s: mpc5121, mpc5125 |
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- reg : Offset and length of the register set for the PSC device |
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- interrupts : <a b> where a is the interrupt number of the |
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PSC FIFO Controller and b is a field that represents an |
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encoding of the sense and level information for the interrupt. |
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Recommended properties : |
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- fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4) |
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- fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4) |
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PSC in SPI mode |
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--------------- |
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Similar to the UART mode a PSC can be operated in SPI mode. The compatible used |
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for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well. |
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The required and recommended properties are identical to the |
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fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible |
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string. |
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fsl,mpc512x-psc-fifo node |
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------------------------- |
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Required properties : |
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- compatible : Should be "fsl,<soc>-psc-fifo" |
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Supported <soc>s: mpc5121, mpc5125 |
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- reg : Offset and length of the register set for the PSC |
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FIFO Controller |
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- interrupts : <a b> where a is the interrupt number of the |
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PSC FIFO Controller and b is a field that represents an |
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encoding of the sense and level information for the interrupt. |
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Recommended properties : |
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- clocks : specifies the clock needed to operate the fifo controller |
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- clock-names : name(s) for the clock(s) listed in clocks |
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Example for a board using PSC0 and PSC1 devices in serial mode: |
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serial@11000 { |
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; |
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cell-index = <0>; |
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reg = <0x11000 0x100>; |
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interrupts = <40 0x8>; |
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interrupt-parent = < &ipic >; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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}; |
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serial@11100 { |
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; |
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cell-index = <1>; |
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reg = <0x11100 0x100>; |
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interrupts = <40 0x8>; |
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interrupt-parent = < &ipic >; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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}; |
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pscfifo@11f00 { |
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compatible = "fsl,mpc5121-psc-fifo"; |
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reg = <0x11f00 0x100>; |
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interrupts = <40 0x8>; |
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interrupt-parent = < &ipic >; |
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};
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