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33 lines
1.4 KiB
33 lines
1.4 KiB
=================================================================== |
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Power Architecture CPU Binding |
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Copyright 2013 Freescale Semiconductor Inc. |
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Power Architecture CPUs in Freescale SOCs are represented in device trees as |
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per the definition in the Devicetree Specification. |
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In addition to the the Devicetree Specification definitions, the properties |
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defined below may be present on CPU nodes. |
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PROPERTIES |
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- fsl,eref-* |
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Usage: optional |
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Value type: <empty> |
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Definition: The EREF (EREF: A Programmer.s Reference Manual for |
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Freescale Power Architecture) defines the architecture for Freescale |
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Power CPUs. The EREF defines some architecture categories not defined |
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by the Power ISA. For these EREF-specific categories, the existence of |
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a property named fsl,eref-[CAT], where [CAT] is the abbreviated category |
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name with all uppercase letters converted to lowercase, indicates that |
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the category is supported by the implementation. |
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- fsl,portid-mapping |
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Usage: optional |
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Value type: <u32> |
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Definition: The Coherency Subdomain ID Port Mapping Registers and |
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Snoop ID Port Mapping registers, which are part of the CoreNet |
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Coherency fabric (CCF), provide a CoreNet Coherency Subdomain |
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ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from |
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these registers should be set if the coresponding CPU should be |
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snooped. This property defines a bitmask which selects the bit |
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that should be set if this cpu should be snooped.
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