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124 lines
3.2 KiB
124 lines
3.2 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/power/fsl,imx-gpc.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Freescale i.MX General Power Controller |
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maintainers: |
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- Philipp Zabel <[email protected]> |
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description: | |
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The i.MX6 General Power Control (GPC) block contains DVFS load tracking |
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counters and Power Gating Control (PGC). |
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The power domains are generic power domain providers as documented in |
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Documentation/devicetree/bindings/power/power-domain.yaml. They are |
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described as subnodes of the power gating controller 'pgc' node of the GPC. |
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IP cores belonging to a power domain should contain a 'power-domains' |
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property that is a phandle pointing to the power domain the device belongs |
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to. |
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properties: |
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compatible: |
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enum: |
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- fsl,imx6q-gpc |
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- fsl,imx6qp-gpc |
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- fsl,imx6sl-gpc |
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- fsl,imx6sx-gpc |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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clock-names: |
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const: ipg |
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pgc: |
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type: object |
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description: list of power domains provided by this controller. |
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patternProperties: |
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"power-domain@[0-9]$": |
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type: object |
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properties: |
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'#power-domain-cells': |
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const: 0 |
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reg: |
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description: | |
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The following DOMAIN_INDEX values are valid for i.MX6Q: |
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ARM_DOMAIN 0 |
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PU_DOMAIN 1 |
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The following additional DOMAIN_INDEX value is valid for i.MX6SL: |
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DISPLAY_DOMAIN 2 |
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The following additional DOMAIN_INDEX value is valid for i.MX6SX: |
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PCI_DOMAIN 3 |
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maxItems: 1 |
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clocks: |
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description: | |
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A number of phandles to clocks that need to be enabled during domain |
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power-up sequencing to ensure reset propagation into devices located |
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inside this power domain. |
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minItems: 1 |
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maxItems: 7 |
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power-supply: true |
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required: |
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- '#power-domain-cells' |
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- reg |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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- pgc |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/imx6qdl-clock.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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gpc@20dc000 { |
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compatible = "fsl,imx6q-gpc"; |
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reg = <0x020dc000 0x4000>; |
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clks IMX6QDL_CLK_IPG>; |
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clock-names = "ipg"; |
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pgc { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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power-domain@0 { |
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reg = <0>; |
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#power-domain-cells = <0>; |
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}; |
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pd_pu: power-domain@1 { |
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reg = <1>; |
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#power-domain-cells = <0>; |
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power-supply = <®_pu>; |
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clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, |
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<&clks IMX6QDL_CLK_GPU3D_SHADER>, |
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<&clks IMX6QDL_CLK_GPU2D_CORE>, |
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<&clks IMX6QDL_CLK_GPU2D_AXI>, |
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<&clks IMX6QDL_CLK_OPENVG_AXI>, |
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<&clks IMX6QDL_CLK_VPU_AXI>; |
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}; |
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}; |
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};
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