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107 lines
2.7 KiB
107 lines
2.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Socionext UniPhier USB3 High-Speed (HS) PHY |
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description: | |
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This describes the devicetree bindings for PHY interfaces built into |
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USB3 controller implemented on Socionext UniPhier SoCs. |
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Although the controller includes High-Speed PHY and Super-Speed PHY, |
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this describes about High-Speed PHY. |
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maintainers: |
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- Kunihiko Hayashi <[email protected]> |
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properties: |
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compatible: |
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enum: |
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- socionext,uniphier-pro5-usb3-hsphy |
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- socionext,uniphier-pxs2-usb3-hsphy |
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- socionext,uniphier-ld20-usb3-hsphy |
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- socionext,uniphier-pxs3-usb3-hsphy |
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reg: |
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maxItems: 1 |
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"#phy-cells": |
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const: 0 |
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clocks: |
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minItems: 1 |
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maxItems: 3 |
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clock-names: |
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oneOf: |
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- const: link # for PXs2 |
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- items: # for PXs3 with phy-ext |
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- const: link |
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- const: phy |
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- const: phy-ext |
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- items: # for others |
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- const: link |
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- const: phy |
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resets: |
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maxItems: 2 |
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reset-names: |
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items: |
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- const: link |
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- const: phy |
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vbus-supply: |
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description: A phandle to the regulator for USB VBUS |
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nvmem-cells: |
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maxItems: 3 |
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description: |
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Phandles to nvmem cell that contains the trimming data. |
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Available only for HS-PHY implemented on LD20 and PXs3, and |
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if unspecified, default value is used. |
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nvmem-cell-names: |
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items: |
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- const: rterm |
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- const: sel_t |
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- const: hs_i |
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description: |
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Should be the following names, which correspond to each nvmem-cells. |
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All of the 3 parameters associated with the above names are |
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required for each port, if any one is omitted, the trimming data |
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of the port will not be set at all. |
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required: |
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- compatible |
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- reg |
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- "#phy-cells" |
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- clocks |
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- clock-names |
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- resets |
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- reset-names |
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additionalProperties: false |
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examples: |
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- | |
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usb-glue@65b00000 { |
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compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x65b00000 0x400>; |
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usb_hsphy0: hs-phy@200 { |
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compatible = "socionext,uniphier-ld20-usb3-hsphy"; |
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reg = <0x200 0x10>; |
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#phy-cells = <0>; |
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clock-names = "link", "phy"; |
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clocks = <&sys_clk 14>, <&sys_clk 16>; |
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reset-names = "link", "phy"; |
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resets = <&sys_rst 14>, <&sys_rst 16>; |
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vbus-supply = <&usb_vbus0>; |
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nvmem-cell-names = "rterm", "sel_t", "hs_i"; |
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; |
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}; |
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};
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