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73 lines
1.7 KiB
73 lines
1.7 KiB
# SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings |
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maintainers: |
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- Helen Koike <[email protected]> |
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- Ezequiel Garcia <[email protected]> |
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description: | |
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The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to |
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the ISP1 (Image Signal Processing unit v1.0) for CSI cameras. |
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properties: |
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compatible: |
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const: rockchip,rk3399-mipi-dphy-rx0 |
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clocks: |
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items: |
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- description: MIPI D-PHY ref clock |
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- description: MIPI D-PHY RX0 cfg clock |
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- description: Video in/out general register file clock |
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clock-names: |
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items: |
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- const: dphy-ref |
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- const: dphy-cfg |
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- const: grf |
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'#phy-cells': |
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const: 0 |
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power-domains: |
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description: Video in/out power domain. |
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maxItems: 1 |
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required: |
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- compatible |
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- clocks |
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- clock-names |
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- '#phy-cells' |
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- power-domains |
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additionalProperties: false |
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examples: |
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- | |
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/* |
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* MIPI D-PHY RX0 use registers in "general register files", it |
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* should be a child of the GRF. |
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* |
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* grf: syscon@ff770000 { |
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* compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; |
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* ... |
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* }; |
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*/ |
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#include <dt-bindings/clock/rk3399-cru.h> |
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#include <dt-bindings/power/rk3399-power.h> |
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mipi_dphy_rx0: mipi-dphy-rx0 { |
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compatible = "rockchip,rk3399-mipi-dphy-rx0"; |
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clocks = <&cru SCLK_MIPIDPHY_REF>, |
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<&cru SCLK_DPHY_RX0_CFG>, |
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<&cru PCLK_VIO_GRF>; |
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clock-names = "dphy-ref", "dphy-cfg", "grf"; |
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power-domains = <&power RK3399_PD_VIO>; |
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#phy-cells = <0>; |
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};
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