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94 lines
2.3 KiB
94 lines
2.3 KiB
MVEBU comphy drivers |
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COMPHY controllers can be found on the following Marvell MVEBU SoCs: |
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* Armada 7k/8k (on the CP110) |
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* Armada 3700 |
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It provides a number of shared PHYs used by various interfaces (network, SATA, |
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USB, PCIe...). |
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Required properties: |
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- compatible: should be one of: |
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* "marvell,comphy-cp110" for Armada 7k/8k |
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* "marvell,comphy-a3700" for Armada 3700 |
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- reg: should contain the COMPHY register(s) location(s) and length(s). |
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* 1 entry for Armada 7k/8k |
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* 4 entries for Armada 3700 along with the corresponding reg-names |
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properties, memory areas are: |
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* Generic COMPHY registers |
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* Lane 1 (PCIe/GbE) |
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* Lane 0 (USB3/GbE) |
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* Lane 2 (SATA/USB3) |
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- marvell,system-controller: should contain a phandle to the system |
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controller node (only for Armada 7k/8k) |
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- #address-cells: should be 1. |
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- #size-cells: should be 0. |
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Optional properlties: |
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- clocks: pointers to the reference clocks for this device (CP110 only), |
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consequently: MG clock, MG Core clock, AXI clock. |
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- clock-names: names of used clocks for CP110 only, must be : |
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"mg_clk", "mg_core_clk" and "axi_clk". |
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A sub-node is required for each comphy lane provided by the comphy. |
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Required properties (child nodes): |
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- reg: COMPHY lane number. |
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- #phy-cells : from the generic PHY bindings, must be 1. Defines the |
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input port to use for a given comphy lane. |
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Examples: |
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cpm_comphy: phy@120000 { |
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compatible = "marvell,comphy-cp110"; |
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reg = <0x120000 0x6000>; |
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marvell,system-controller = <&cpm_syscon0>; |
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clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>, |
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<&CP110_LABEL(clk) 1 18>; |
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clock-names = "mg_clk", "mg_core_clk", "axi_clk"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpm_comphy0: phy@0 { |
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reg = <0>; |
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#phy-cells = <1>; |
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}; |
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cpm_comphy1: phy@1 { |
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reg = <1>; |
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#phy-cells = <1>; |
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}; |
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}; |
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comphy: phy@18300 { |
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compatible = "marvell,comphy-a3700"; |
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reg = <0x18300 0x300>, |
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<0x1F000 0x400>, |
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<0x5C000 0x400>, |
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<0xe0178 0x8>; |
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reg-names = "comphy", |
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"lane1_pcie_gbe", |
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"lane0_usb3_gbe", |
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"lane2_sata_usb3"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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comphy0: phy@0 { |
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reg = <0>; |
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#phy-cells = <1>; |
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}; |
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comphy1: phy@1 { |
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reg = <1>; |
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#phy-cells = <1>; |
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}; |
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comphy2: phy@2 { |
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reg = <2>; |
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#phy-cells = <1>; |
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}; |
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};
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