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260 lines
7.1 KiB
260 lines
7.1 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (c) 2020 MediaTek |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: MediaTek T-PHY Controller Device Tree Bindings |
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maintainers: |
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- Chunfeng Yun <[email protected]> |
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description: | |
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The T-PHY controller supports physical layer functionality for a number of |
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controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. |
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Layout differences of banks between T-PHY V1 (mt8173/mt2701) and |
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T-PHY V2 (mt2712) when works on USB mode: |
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----------------------------------- |
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Version 1: |
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port offset bank |
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shared 0x0000 SPLLC |
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0x0100 FMREG |
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u2 port0 0x0800 U2PHY_COM |
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u3 port0 0x0900 U3PHYD |
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0x0a00 U3PHYD_BANK2 |
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0x0b00 U3PHYA |
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0x0c00 U3PHYA_DA |
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u2 port1 0x1000 U2PHY_COM |
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u3 port1 0x1100 U3PHYD |
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0x1200 U3PHYD_BANK2 |
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0x1300 U3PHYA |
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0x1400 U3PHYA_DA |
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u2 port2 0x1800 U2PHY_COM |
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... |
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Version 2: |
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port offset bank |
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u2 port0 0x0000 MISC |
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0x0100 FMREG |
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0x0300 U2PHY_COM |
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u3 port0 0x0700 SPLLC |
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0x0800 CHIP |
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0x0900 U3PHYD |
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0x0a00 U3PHYD_BANK2 |
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0x0b00 U3PHYA |
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0x0c00 U3PHYA_DA |
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u2 port1 0x1000 MISC |
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0x1100 FMREG |
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0x1300 U2PHY_COM |
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u3 port1 0x1700 SPLLC |
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0x1800 CHIP |
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0x1900 U3PHYD |
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0x1a00 U3PHYD_BANK2 |
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0x1b00 U3PHYA |
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0x1c00 U3PHYA_DA |
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u2 port2 0x2000 MISC |
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... |
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SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back |
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into each port; a new bank MISC for u2 ports and CHIP for u3 ports are |
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added on V2. |
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properties: |
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$nodename: |
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pattern: "^t-phy@[0-9a-f]+$" |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- mediatek,mt2701-tphy |
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- mediatek,mt7623-tphy |
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- mediatek,mt7622-tphy |
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- mediatek,mt8516-tphy |
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- const: mediatek,generic-tphy-v1 |
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- items: |
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- enum: |
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- mediatek,mt2712-tphy |
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- mediatek,mt7629-tphy |
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- mediatek,mt8183-tphy |
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- const: mediatek,generic-tphy-v2 |
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- const: mediatek,mt2701-u3phy |
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deprecated: true |
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- const: mediatek,mt2712-u3phy |
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deprecated: true |
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- const: mediatek,mt8173-u3phy |
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reg: |
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description: |
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Register shared by multiple ports, exclude port's private register. |
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It is needed for T-PHY V1, such as mt2701 and mt8173, but not for |
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T-PHY V2, such as mt2712. |
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maxItems: 1 |
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"#address-cells": |
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enum: [1, 2] |
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"#size-cells": |
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enum: [1, 2] |
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# Used with non-empty value if optional 'reg' is not provided. |
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# The format of the value is an arbitrary number of triplets of |
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# (child-bus-address, parent-bus-address, length). |
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ranges: true |
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mediatek,src-ref-clk-mhz: |
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description: |
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Frequency of reference clock for slew rate calibrate |
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default: 26 |
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mediatek,src-coef: |
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description: |
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Coefficient for slew rate calibrate, depends on SoC process |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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default: 28 |
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# Required child node: |
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patternProperties: |
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"^usb-phy@[0-9a-f]+$": |
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type: object |
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description: |
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A sub-node is required for each port the controller provides. |
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Address range information including the usual 'reg' property |
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is used inside these nodes to describe the controller's topology. |
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properties: |
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reg: |
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maxItems: 1 |
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clocks: |
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minItems: 1 |
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maxItems: 2 |
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items: |
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- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) |
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- description: Reference clock of analog phy |
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description: |
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Uses both clocks if the clock of analog and digital phys are |
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separated, otherwise uses "ref" clock only if needed. |
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clock-names: |
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minItems: 1 |
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maxItems: 2 |
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items: |
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- const: ref |
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- const: da_ref |
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"#phy-cells": |
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const: 1 |
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description: | |
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The cells contain the following arguments. |
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- description: The PHY type |
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enum: |
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- PHY_TYPE_USB2 |
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- PHY_TYPE_USB3 |
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- PHY_TYPE_PCIE |
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- PHY_TYPE_SATA |
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# The following optional vendor properties are only for debug or HQA test |
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mediatek,eye-src: |
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description: |
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The value of slew rate calibrate (U2 phy) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 7 |
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mediatek,eye-vrt: |
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description: |
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The selection of VRT reference voltage (U2 phy) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 7 |
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mediatek,eye-term: |
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description: |
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The selection of HS_TX TERM reference voltage (U2 phy) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 7 |
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mediatek,intr: |
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description: |
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The selection of internal resistor (U2 phy) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 31 |
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mediatek,discth: |
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description: |
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The selection of disconnect threshold (U2 phy) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 15 |
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mediatek,bc12: |
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description: |
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Specify the flag to enable BC1.2 if support it |
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type: boolean |
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required: |
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- reg |
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- "#phy-cells" |
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additionalProperties: false |
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required: |
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- compatible |
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- "#address-cells" |
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- "#size-cells" |
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- ranges |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/mt8173-clk.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/phy/phy.h> |
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usb@11271000 { |
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compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; |
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reg = <0x11271000 0x3000>, <0x11280700 0x0100>; |
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reg-names = "mac", "ippc"; |
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phys = <&u2port0 PHY_TYPE_USB2>, |
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<&u3port0 PHY_TYPE_USB3>, |
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<&u2port1 PHY_TYPE_USB2>; |
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_USB30_SEL>; |
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clock-names = "sys_ck"; |
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}; |
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t-phy@11290000 { |
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compatible = "mediatek,mt8173-u3phy"; |
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reg = <0x11290000 0x800>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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u2port0: usb-phy@11290800 { |
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reg = <0x11290800 0x100>; |
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clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; |
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clock-names = "ref", "da_ref"; |
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#phy-cells = <1>; |
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}; |
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u3port0: usb-phy@11290900 { |
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reg = <0x11290900 0x700>; |
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clocks = <&clk26m>; |
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clock-names = "ref"; |
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#phy-cells = <1>; |
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}; |
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u2port1: usb-phy@11291000 { |
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reg = <0x11291000 0x100>; |
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#phy-cells = <1>; |
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}; |
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}; |
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...
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