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92 lines
1.9 KiB
92 lines
1.9 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (c) 2020 MediaTek |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding |
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maintainers: |
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- Chun-Kuang Hu <[email protected]> |
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- Philipp Zabel <[email protected]> |
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- Chunfeng Yun <[email protected]> |
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description: | |
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The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel |
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output and drives the HDMI pads. |
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properties: |
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$nodename: |
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pattern: "^hdmi-phy@[0-9a-f]+$" |
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compatible: |
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enum: |
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- mediatek,mt2701-hdmi-phy |
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- mediatek,mt7623-hdmi-phy |
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- mediatek,mt8173-hdmi-phy |
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reg: |
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maxItems: 1 |
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clocks: |
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items: |
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- description: PLL reference clock |
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clock-names: |
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items: |
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- const: pll_ref |
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clock-output-names: |
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items: |
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- const: hdmitx_dig_cts |
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"#phy-cells": |
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const: 0 |
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"#clock-cells": |
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const: 0 |
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mediatek,ibias: |
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description: |
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TX DRV bias current for < 1.65Gbps |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0 |
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maximum: 63 |
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default: 0xa |
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mediatek,ibias_up: |
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description: |
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TX DRV bias current for >= 1.65Gbps |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 0 |
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maximum: 63 |
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default: 0x1c |
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required: |
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- compatible |
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- reg |
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- clocks |
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- clock-names |
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- clock-output-names |
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- "#phy-cells" |
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- "#clock-cells" |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/mt8173-clk.h> |
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hdmi_phy: hdmi-phy@10209100 { |
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compatible = "mediatek,mt8173-hdmi-phy"; |
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reg = <0x10209100 0x24>; |
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clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; |
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clock-names = "pll_ref"; |
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clock-output-names = "hdmitx_dig_cts"; |
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mediatek,ibias = <0xa>; |
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mediatek,ibias_up = <0x1c>; |
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#clock-cells = <0>; |
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#phy-cells = <0>; |
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}; |
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...
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