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80 lines
3.5 KiB
80 lines
3.5 KiB
XILINX AXI ETHERNET Device Tree Bindings |
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Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core |
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provides connectivity to an external ethernet PHY supporting different |
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interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two |
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segments of memory for buffering TX and RX, as well as the capability of |
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offloading TX/RX checksum calculation off the processor. |
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Management configuration is done through the AXI interface, while payload is |
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sent and received through means of an AXI DMA controller. This driver |
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includes the DMA driver code, so this driver is incompatible with AXI DMA |
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driver. |
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For more details about mdio please refer phy.txt file in the same directory. |
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Required properties: |
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- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", |
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"xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" |
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- reg : Address and length of the IO space, as well as the address |
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and length of the AXI DMA controller IO space, unless |
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axistream-connected is specified, in which case the reg |
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attribute of the node referenced by it is used. |
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- interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA, |
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and optionally Ethernet core. If axistream-connected is |
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specified, the TX/RX DMA interrupts should be on that node |
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instead, and only the Ethernet core interrupt is optionally |
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specified here. |
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- phy-handle : Should point to the external phy device. |
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See ethernet.txt file in the same directory. |
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- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware |
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Optional properties: |
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- phy-mode : See ethernet.txt |
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- xlnx,phy-type : Deprecated, do not use, but still accepted in preference |
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to phy-mode. |
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- xlnx,txcsum : 0 or empty for disabling TX checksum offload, |
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1 to enable partial TX checksum offload, |
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2 to enable full TX checksum offload |
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- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload |
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- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to |
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support both 1000BaseX and SGMII modes. If set, the phy-mode |
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should be set to match the mode selected on core reset (i.e. |
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by the basex_or_sgmii core input line). |
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- clocks : AXI bus clock for the device. Refer to common clock bindings. |
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Used to calculate MDIO clock divisor. If not specified, it is |
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auto-detected from the CPU clock (but only on platforms where |
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this is possible). New device trees should specify this - the |
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auto detection is only for backward compatibility. |
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- axistream-connected: Reference to another node which contains the resources |
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for the AXI DMA controller used by this device. |
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If this is specified, the DMA-related resources from that |
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device (DMA registers and DMA TX/RX interrupts) rather |
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than this one will be used. |
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- mdio : Child node for MDIO bus. Must be defined if PHY access is |
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required through the core's MDIO interface (i.e. always, |
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unless the PHY is accessed through a different bus). |
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Example: |
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axi_ethernet_eth: ethernet@40c00000 { |
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compatible = "xlnx,axi-ethernet-1.00.a"; |
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device_type = "network"; |
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interrupt-parent = <µblaze_0_axi_intc>; |
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interrupts = <2 0 1>; |
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clocks = <&axi_clk>; |
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phy-mode = "mii"; |
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reg = <0x40c00000 0x40000 0x50c00000 0x40000>; |
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xlnx,rxcsum = <0x2>; |
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xlnx,rxmem = <0x800>; |
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xlnx,txcsum = <0x2>; |
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phy-handle = <&phy0>; |
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axi_ethernetlite_0_mdio: mdio { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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phy0: phy@0 { |
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device_type = "ethernet-phy"; |
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reg = <1>; |
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}; |
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}; |
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};
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