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26 lines
770 B
26 lines
770 B
Microsemi MII Management Controller (MIIM) / MDIO |
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Properties: |
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- compatible: must be "mscc,ocelot-miim" |
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- reg: The base address of the MDIO bus controller register bank. Optionally, a |
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second register bank can be defined if there is an associated reset register |
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for internal PHYs |
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- #address-cells: Must be <1>. |
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- #size-cells: Must be <0>. MDIO addresses have no size component. |
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- interrupts: interrupt specifier (refer to the interrupt binding) |
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Typically an MDIO bus might have several children. |
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Example: |
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mdio@107009c { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "mscc,ocelot-miim"; |
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reg = <0x107009c 0x36>, <0x10700f0 0x8>; |
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interrupts = <14>; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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};
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