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97 lines
3.4 KiB
97 lines
3.4 KiB
Device tree bindings for Ethernet chip connected to TI GPMC |
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Besides being used to interface with external memory devices, the |
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General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices |
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such as ethernet controllers to processors using the TI GPMC as a data bus. |
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Ethernet controllers connected to TI GPMC are represented as child nodes of |
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the GPMC controller with an "ethernet" name. |
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All timing relevant properties as well as generic GPMC child properties are |
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explained in a separate documents. Please refer to |
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Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt |
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For the properties relevant to the ethernet controller connected to the GPMC |
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refer to the binding documentation of the device. For example, the documentation |
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for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt |
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Child nodes need to specify the GPMC bus address width using the "bank-width" |
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property but is possible that an ethernet controller also has a property to |
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specify the I/O registers address width. Even when the GPMC has a maximum 16-bit |
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address width, it supports devices with 32-bit word registers. |
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For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an |
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OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". |
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Required properties: |
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- bank-width: Address width of the device in bytes. GPMC supports 8-bit |
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and 16-bit devices and so must be either 1 or 2 bytes. |
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- compatible: Compatible string property for the ethernet child device. |
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- gpmc,cs-on-ns: Chip-select assertion time |
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- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads |
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- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes |
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- gpmc,oe-on-ns: Output-enable assertion time |
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- gpmc,oe-off-ns: Output-enable de-assertion time |
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- gpmc,we-on-ns: Write-enable assertion time |
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- gpmc,we-off-ns: Write-enable de-assertion time |
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- gpmc,access-ns: Start cycle to first data capture (read access) |
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- gpmc,rd-cycle-ns: Total read cycle time |
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- gpmc,wr-cycle-ns: Total write cycle time |
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- reg: Chip-select, base address (relative to chip-select) |
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and size of the memory mapped for the device. |
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Note that base address will be typically 0 as this |
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is the start of the chip-select. |
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Optional properties: |
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- gpmc,XXX Additional GPMC timings and settings parameters. See |
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Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt |
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Example: |
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gpmc: gpmc@6e000000 { |
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compatible = "ti,omap3430-gpmc"; |
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ti,hwmods = "gpmc"; |
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reg = <0x6e000000 0x1000>; |
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interrupts = <20>; |
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gpmc,num-cs = <8>; |
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gpmc,num-waitpins = <4>; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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ranges = <5 0 0x2c000000 0x1000000>; |
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ethernet@5,0 { |
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compatible = "smsc,lan9221", "smsc,lan9115"; |
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reg = <5 0 0xff>; |
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bank-width = <2>; |
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gpmc,mux-add-data; |
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gpmc,cs-on-ns = <0>; |
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gpmc,cs-rd-off-ns = <186>; |
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gpmc,cs-wr-off-ns = <186>; |
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gpmc,adv-on-ns = <12>; |
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gpmc,adv-rd-off-ns = <48>; |
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gpmc,adv-wr-off-ns = <48>; |
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gpmc,oe-on-ns = <54>; |
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gpmc,oe-off-ns = <168>; |
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gpmc,we-on-ns = <54>; |
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gpmc,we-off-ns = <168>; |
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gpmc,rd-cycle-ns = <186>; |
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gpmc,wr-cycle-ns = <186>; |
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gpmc,access-ns = <114>; |
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gpmc,page-burst-access-ns = <6>; |
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gpmc,bus-turnaround-ns = <12>; |
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gpmc,cycle2cycle-delay-ns = <18>; |
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gpmc,wr-data-mux-bus-ns = <90>; |
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gpmc,wr-access-ns = <186>; |
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gpmc,cycle2cycle-samecsen; |
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gpmc,cycle2cycle-diffcsen; |
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interrupt-parent = <&gpio6>; |
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interrupts = <16>; |
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vmmc-supply = <&vddvario>; |
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vmmc_aux-supply = <&vdd33a>; |
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reg-io-width = <4>; |
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smsc,save-mac-address; |
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}; |
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};
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