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32 lines
986 B
32 lines
986 B
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller |
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The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit |
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bus width configurations. |
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The Zynq DDR ECC controller has an optional ECC support in half-bus width |
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(16-bit) configuration. |
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These both ECC controllers correct single bit ECC errors and detect double bit |
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ECC errors. |
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Required properties: |
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- compatible: One of: |
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- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller |
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- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller |
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- reg: Should contain DDR controller registers location and length. |
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Required properties for "xlnx,zynqmp-ddrc-2.40a": |
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- interrupts: Property with a value describing the interrupt number. |
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Example: |
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memory-controller@f8006000 { |
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compatible = "xlnx,zynq-ddrc-a05"; |
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reg = <0xf8006000 0x1000>; |
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}; |
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mc: memory-controller@fd070000 { |
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compatible = "xlnx,zynqmp-ddrc-2.40a"; |
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reg = <0x0 0xfd070000 0x0 0x30000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 112 4>; |
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};
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