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84 lines
3.5 KiB
84 lines
3.5 KiB
* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device |
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The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM |
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memory chips are connected. The driver is to monitor the controller in runtime |
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and switch frequency and voltage. To monitor the usage of the controller in |
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runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which |
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is able to measure the current load of the memory. |
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When 'userspace' governor is used for the driver, an application is able to |
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switch the DMC and memory frequency. |
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Required properties for DMC device for Exynos5422: |
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- compatible: Should be "samsung,exynos5422-dmc". |
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- clocks : list of clock specifiers, must contain an entry for each |
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required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, |
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CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, |
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CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, |
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- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", |
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"fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", |
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"mout_mclk_cdrex" entries |
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- devfreq-events : phandles for PPMU devices connected to this DMC. |
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- vdd-supply : phandle for voltage regulator which is connected. |
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- reg : registers of two CDREX controllers. |
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- operating-points-v2 : phandle for OPPs described in v2 definition. |
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- device-handle : phandle of the connected DRAM memory device. For more |
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information please refer to documentation file: |
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Documentation/devicetree/bindings/ddr/lpddr3.txt |
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- devfreq-events : phandles of the PPMU events used by the controller. |
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- samsung,syscon-clk : phandle of the clock register set used by the controller, |
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these registers are used for enabling a 'pause' feature and are not |
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exposed by clock framework but they must be used in a safe way. |
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The register offsets are in the driver code and specyfic for this SoC |
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type. |
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Optional properties for DMC device for Exynos5422: |
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- interrupt-parent : The parent interrupt controller. |
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- interrupts : Contains the IRQ line numbers for the DMC internal performance |
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event counters in DREX0 and DREX1 channels. Align with specification of the |
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interrupt line(s) in the interrupt-parent controller. |
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- interrupt-names : IRQ names "drex_0" and "drex_1", the order should be the |
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same as in the 'interrupts' list above. |
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Example: |
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ppmu_dmc0_0: ppmu@10d00000 { |
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compatible = "samsung,exynos-ppmu"; |
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reg = <0x10d00000 0x2000>; |
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clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; |
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clock-names = "ppmu"; |
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events { |
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ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { |
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event-name = "ppmu-event3-dmc0_0"; |
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}; |
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}; |
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}; |
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dmc: memory-controller@10c20000 { |
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compatible = "samsung,exynos5422-dmc"; |
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reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>; |
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clocks = <&clock CLK_FOUT_SPLL>, |
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<&clock CLK_MOUT_SCLK_SPLL>, |
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<&clock CLK_FF_DOUT_SPLL2>, |
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<&clock CLK_FOUT_BPLL>, |
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<&clock CLK_MOUT_BPLL>, |
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<&clock CLK_SCLK_BPLL>, |
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<&clock CLK_MOUT_MX_MSPLL_CCORE>, |
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<&clock CLK_MOUT_MCLK_CDREX>; |
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clock-names = "fout_spll", |
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"mout_sclk_spll", |
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"ff_dout_spll2", |
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"fout_bpll", |
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"mout_bpll", |
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"sclk_bpll", |
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"mout_mx_mspll_ccore", |
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"mout_mclk_cdrex"; |
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operating-points-v2 = <&dmc_opp_table>; |
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devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, |
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<&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; |
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device-handle = <&samsung_K3QF2F20DB>; |
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vdd-supply = <&buck1_reg>; |
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samsung,syscon-clk = <&clock>; |
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interrupt-parent = <&combiner>; |
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interrupts = <16 0>, <16 1>; |
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interrupt-names = "drex_0", "drex_1"; |
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};
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