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21 lines
668 B
21 lines
668 B
NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) |
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Required properties: |
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- compatible : "nvidia,tegra30-smmu" |
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- reg : Should contain 3 register banks(address and length) for each |
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of the SMMU register blocks. |
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- interrupts : Should contain MC General interrupt. |
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- nvidia,#asids : # of ASIDs |
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- dma-window : IOVA start address and length. |
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- nvidia,ahb : phandle to the ahb bus connected to SMMU. |
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Example: |
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smmu { |
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compatible = "nvidia,tegra30-smmu"; |
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reg = <0x7000f010 0x02c |
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0x7000f1f0 0x010 |
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0x7000f228 0x05c>; |
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nvidia,#asids = <4>; /* # of ASIDs */ |
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dma-window = <0 0x40000000>; /* IOVA start & length */ |
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nvidia,ahb = <&ahb>; |
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};
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