mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
383 lines
12 KiB
383 lines
12 KiB
Altera SoCFPGA ECC Manager |
|
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. |
|
The ECC Manager counts and corrects single bit errors and counts/handles |
|
double bit errors which are uncorrectable. |
|
|
|
Cyclone5 and Arria5 ECC Manager |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-ecc-manager" |
|
- #address-cells: must be 1 |
|
- #size-cells: must be 1 |
|
- ranges : standard definition, should translate from local addresses |
|
|
|
Subcomponents: |
|
|
|
L2 Cache ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-l2-ecc" |
|
- reg : Address and size for ECC error interrupt clear registers. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt. Note the rising edge type. |
|
|
|
On Chip RAM ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-ocram-ecc" |
|
- reg : Address and size for ECC error interrupt clear registers. |
|
- iram : phandle to On-Chip RAM definition. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt. Note the rising edge type. |
|
|
|
Example: |
|
|
|
eccmgr: eccmgr@ffd08140 { |
|
compatible = "altr,socfpga-ecc-manager"; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
ranges; |
|
|
|
l2-ecc@ffd08140 { |
|
compatible = "altr,socfpga-l2-ecc"; |
|
reg = <0xffd08140 0x4>; |
|
interrupts = <0 36 1>, <0 37 1>; |
|
}; |
|
|
|
ocram-ecc@ffd08144 { |
|
compatible = "altr,socfpga-ocram-ecc"; |
|
reg = <0xffd08144 0x4>; |
|
iram = <&ocram>; |
|
interrupts = <0 178 1>, <0 179 1>; |
|
}; |
|
}; |
|
|
|
Arria10 SoCFPGA ECC Manager |
|
The Arria10 SoC ECC Manager handles the IRQs for each peripheral |
|
in a shared register instead of individual IRQs like the Cyclone5 |
|
and Arria5. Therefore the device tree is different as well. |
|
|
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-a10-ecc-manager" |
|
- altr,sysgr-syscon : phandle to Arria10 System Manager Block |
|
containing the ECC manager registers. |
|
- #address-cells: must be 1 |
|
- #size-cells: must be 1 |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt. |
|
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller |
|
- #interrupt-cells : must be set to 2. |
|
- ranges : standard definition, should translate from local addresses |
|
|
|
Subcomponents: |
|
|
|
L2 Cache ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-a10-l2-ecc" |
|
- reg : Address and size for ECC error interrupt clear registers. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
On-Chip RAM ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-a10-ocram-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
Ethernet FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-eth-mac-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent Ethernet node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
NAND FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-nand-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent NAND node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
DMA FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-dma-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent DMA node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
USB FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-usb-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent USB node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
QSPI FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-qspi-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent QSPI node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order. |
|
|
|
SDMMC FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-sdmmc-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent SD/MMC node. |
|
- interrupts : Should be single bit error interrupt, then double bit error |
|
interrupt, in this order for port A, and then single bit error interrupt, |
|
then double bit error interrupt in this order for port B. |
|
|
|
Example: |
|
|
|
eccmgr: eccmgr@ffd06000 { |
|
compatible = "altr,socfpga-a10-ecc-manager"; |
|
altr,sysmgr-syscon = <&sysmgr>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, |
|
<0 0 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
ranges; |
|
|
|
l2-ecc@ffd06010 { |
|
compatible = "altr,socfpga-a10-l2-ecc"; |
|
reg = <0xffd06010 0x4>; |
|
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, |
|
<32 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
ocram-ecc@ff8c3000 { |
|
compatible = "altr,socfpga-a10-ocram-ecc"; |
|
reg = <0xff8c3000 0x90>; |
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, |
|
<33 IRQ_TYPE_LEVEL_HIGH> ; |
|
}; |
|
|
|
emac0-rx-ecc@ff8c0800 { |
|
compatible = "altr,socfpga-eth-mac-ecc"; |
|
reg = <0xff8c0800 0x400>; |
|
altr,ecc-parent = <&gmac0>; |
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, |
|
<36 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
emac0-tx-ecc@ff8c0c00 { |
|
compatible = "altr,socfpga-eth-mac-ecc"; |
|
reg = <0xff8c0c00 0x400>; |
|
altr,ecc-parent = <&gmac0>; |
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, |
|
<37 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nand-buf-ecc@ff8c2000 { |
|
compatible = "altr,socfpga-nand-ecc"; |
|
reg = <0xff8c2000 0x400>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, |
|
<43 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nand-rd-ecc@ff8c2400 { |
|
compatible = "altr,socfpga-nand-ecc"; |
|
reg = <0xff8c2400 0x400>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, |
|
<45 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nand-wr-ecc@ff8c2800 { |
|
compatible = "altr,socfpga-nand-ecc"; |
|
reg = <0xff8c2800 0x400>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, |
|
<44 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
dma-ecc@ff8c8000 { |
|
compatible = "altr,socfpga-dma-ecc"; |
|
reg = <0xff8c8000 0x400>; |
|
altr,ecc-parent = <&pdma>; |
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, |
|
<42 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
usb0-ecc@ff8c8800 { |
|
compatible = "altr,socfpga-usb-ecc"; |
|
reg = <0xff8c8800 0x400>; |
|
altr,ecc-parent = <&usb0>; |
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, |
|
<34 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
qspi-ecc@ff8c8400 { |
|
compatible = "altr,socfpga-qspi-ecc"; |
|
reg = <0xff8c8400 0x400>; |
|
altr,ecc-parent = <&qspi>; |
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, |
|
<46 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
sdmmc-ecc@ff8c2c00 { |
|
compatible = "altr,socfpga-sdmmc-ecc"; |
|
reg = <0xff8c2c00 0x400>; |
|
altr,ecc-parent = <&mmc>; |
|
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, |
|
<47 IRQ_TYPE_LEVEL_HIGH>, |
|
<16 IRQ_TYPE_LEVEL_HIGH>, |
|
<48 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
}; |
|
|
|
Stratix10 SoCFPGA ECC Manager (ARM64) |
|
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral |
|
in a shared register similar to the Arria10. However, Stratix10 ECC |
|
requires access to registers that can only be read from Secure Monitor |
|
with SMC calls. Therefore the device tree is slightly different. Note |
|
that only 1 interrupt is sent in Stratix10 because the double bit errors |
|
are treated as SErrors in ARM64 instead of IRQs in ARM32. |
|
|
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-ecc-manager" |
|
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block |
|
containing the ECC manager registers. |
|
- interrupts : Should be single bit error interrupt. |
|
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller |
|
- #interrupt-cells : must be set to 2. |
|
- #address-cells: must be 1 |
|
- #size-cells: must be 1 |
|
- ranges : standard definition, should translate from local addresses |
|
|
|
Subcomponents: |
|
|
|
SDRAM ECC |
|
Required Properties: |
|
- compatible : Should be "altr,sdram-edac-s10" |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
On-Chip RAM ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-ocram-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent OCRAM node. |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
Ethernet FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent Ethernet node. |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
NAND FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-nand-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent NAND node. |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
DMA FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-dma-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent DMA node. |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
USB FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-usb-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent USB node. |
|
- interrupts : Should be single bit error interrupt. |
|
|
|
SDMMC FIFO ECC |
|
Required Properties: |
|
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc" |
|
- reg : Address and size for ECC block registers. |
|
- altr,ecc-parent : phandle to parent SD/MMC node. |
|
- interrupts : Should be single bit error interrupt for port A |
|
and then single bit error interrupt for port B. |
|
|
|
Example: |
|
|
|
eccmgr { |
|
compatible = "altr,socfpga-s10-ecc-manager"; |
|
altr,sysmgr-syscon = <&sysmgr>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
interrupts = <0 15 4>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
ranges; |
|
|
|
sdramedac { |
|
compatible = "altr,sdram-edac-s10"; |
|
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
ocram-ecc@ff8cc000 { |
|
compatible = "altr,socfpga-s10-ocram-ecc"; |
|
reg = <ff8cc000 0x100>; |
|
altr,ecc-parent = <&ocram>; |
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
emac0-rx-ecc@ff8c0000 { |
|
compatible = "altr,socfpga-s10-eth-mac-ecc"; |
|
reg = <0xff8c0000 0x100>; |
|
altr,ecc-parent = <&gmac0>; |
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
emac0-tx-ecc@ff8c0400 { |
|
compatible = "altr,socfpga-s10-eth-mac-ecc"; |
|
reg = <0xff8c0400 0x100>; |
|
altr,ecc-parent = <&gmac0>; |
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>' |
|
}; |
|
|
|
nand-buf-ecc@ff8c8000 { |
|
compatible = "altr,socfpga-s10-nand-ecc"; |
|
reg = <0xff8c8000 0x100>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nand-rd-ecc@ff8c8400 { |
|
compatible = "altr,socfpga-s10-nand-ecc"; |
|
reg = <0xff8c8400 0x100>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
nand-wr-ecc@ff8c8800 { |
|
compatible = "altr,socfpga-s10-nand-ecc"; |
|
reg = <0xff8c8800 0x100>; |
|
altr,ecc-parent = <&nand>; |
|
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
dma-ecc@ff8c9000 { |
|
compatible = "altr,socfpga-s10-dma-ecc"; |
|
reg = <0xff8c9000 0x100>; |
|
altr,ecc-parent = <&pdma>; |
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
usb0-ecc@ff8c4000 { |
|
compatible = "altr,socfpga-s10-usb-ecc"; |
|
reg = <0xff8c4000 0x100>; |
|
altr,ecc-parent = <&usb0>; |
|
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
sdmmc-ecc@ff8c8c00 { |
|
compatible = "altr,socfpga-s10-sdmmc-ecc"; |
|
reg = <0xff8c8c00 0x100>; |
|
altr,ecc-parent = <&mmc>; |
|
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, |
|
<15 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
};
|
|
|