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28 lines
811 B
28 lines
811 B
Aspeed BMC SoC EDAC node |
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The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error |
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correction check). |
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The memory controller supports SECDED (single bit error correction, double bit |
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error detection) and single bit error auto scrubbing by reserving 8 bits for |
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every 64 bit word (effectively reducing available memory to 8/9). |
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Note, the bootloader must configure ECC mode in the memory controller. |
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Required properties: |
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- compatible: should be one of |
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- "aspeed,ast2400-sdram-edac" |
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- "aspeed,ast2500-sdram-edac" |
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- "aspeed,ast2600-sdram-edac" |
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- reg: sdram controller register set should be <0x1e6e0000 0x174> |
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- interrupts: should be AVIC interrupt #0 |
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Example: |
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edac: sdram@1e6e0000 { |
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compatible = "aspeed,ast2500-sdram-edac"; |
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reg = <0x1e6e0000 0x174>; |
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interrupts = <0>; |
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};
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