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26 lines
872 B
26 lines
872 B
Xilinx ZynqMP DMA engine, it does support memory to memory transfers, |
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memory to device and device to memory transfers. It also has flow |
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control and rate control support for slave/peripheral dma access. |
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Required properties: |
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- compatible : Should be "xlnx,zynqmp-dma-1.0" |
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- reg : Memory map for gdma/adma module access. |
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- interrupts : Should contain DMA channel interrupt. |
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- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 |
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- clock-names : List of input clocks "clk_main", "clk_apb" |
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(see clock bindings for details) |
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Optional properties: |
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- dma-coherent : Present if dma operations are coherent. |
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Example: |
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++++++++ |
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fpd_dma_chan1: dma@fd500000 { |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xFD500000 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 117 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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dma-coherent; |
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};
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