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126 lines
3.0 KiB
126 lines
3.0 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Synopsys DesignWare AXI DMA Controller |
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maintainers: |
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- Eugeniy Paltsev <[email protected]> |
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- Jee Heng Sia <[email protected]> |
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description: |
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Synopsys DesignWare AXI DMA Controller DT Binding |
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allOf: |
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- $ref: "dma-controller.yaml#" |
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properties: |
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compatible: |
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enum: |
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- snps,axi-dma-1.01a |
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- intel,kmb-axi-dma |
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reg: |
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minItems: 1 |
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items: |
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- description: Address range of the DMAC registers |
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- description: Address range of the DMAC APB registers |
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reg-names: |
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items: |
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- const: axidma_ctrl_regs |
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- const: axidma_apb_regs |
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interrupts: |
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maxItems: 1 |
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clocks: |
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items: |
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- description: Bus Clock |
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- description: Module Clock |
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clock-names: |
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items: |
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- const: core-clk |
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- const: cfgr-clk |
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'#dma-cells': |
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const: 1 |
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dma-channels: |
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minimum: 1 |
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maximum: 8 |
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snps,dma-masters: |
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description: | |
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Number of AXI masters supported by the hardware. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [1, 2] |
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snps,data-width: |
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description: | |
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AXI data width supported by hardware. |
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(0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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enum: [0, 1, 2, 3, 4, 5, 6] |
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snps,priority: |
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description: | |
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Channel priority specifier associated with the DMA channels. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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minItems: 1 |
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maxItems: 8 |
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snps,block-size: |
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description: | |
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Channel block size specifier associated with the DMA channels. |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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minItems: 1 |
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maxItems: 8 |
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snps,axi-max-burst-len: |
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description: | |
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Restrict master AXI burst length by value specified in this property. |
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If this property is missing the maximum AXI burst length supported by |
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DMAC is used. |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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minimum: 1 |
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maximum: 256 |
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required: |
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- compatible |
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- reg |
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- clocks |
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- clock-names |
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- interrupts |
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- '#dma-cells' |
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- dma-channels |
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- snps,dma-masters |
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- snps,data-width |
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- snps,priority |
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- snps,block-size |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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/* example with snps,dw-axi-dmac */ |
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dmac: dma-controller@80000 { |
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compatible = "snps,axi-dma-1.01a"; |
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reg = <0x80000 0x400>; |
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clocks = <&core_clk>, <&cfgr_clk>; |
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clock-names = "core-clk", "cfgr-clk"; |
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interrupt-parent = <&intc>; |
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interrupts = <27>; |
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#dma-cells = <1>; |
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dma-channels = <4>; |
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snps,dma-masters = <2>; |
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snps,data-width = <3>; |
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snps,block-size = <4096 4096 4096 4096>; |
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snps,priority = <0 1 2 3>; |
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snps,axi-max-burst-len = <16>; |
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};
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