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179 lines
5.0 KiB
179 lines
5.0 KiB
# SPDX-License-Identifier: GPL-2.0-only |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Synopsys Designware DMA Controller |
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maintainers: |
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- Viresh Kumar <[email protected]> |
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- Andy Shevchenko <[email protected]> |
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allOf: |
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- $ref: "dma-controller.yaml#" |
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properties: |
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compatible: |
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const: snps,dma-spear1340 |
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"#dma-cells": |
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minimum: 3 |
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maximum: 4 |
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description: | |
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First cell is a phandle pointing to the DMA controller. Second one is |
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the DMA request line number. Third cell is the memory master identifier |
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for transfers on dynamically allocated channel. Fourth cell is the |
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peripheral master identifier for transfers on an allocated channel. Fifth |
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cell is an optional mask of the DMA channels permitted to be allocated |
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for the corresponding client device. |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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clock-names: |
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description: AHB interface reference clock. |
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const: hclk |
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dma-channels: |
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description: | |
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Number of DMA channels supported by the controller. In case if |
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not specified the driver will try to auto-detect this and |
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the rest of the optional parameters. |
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minimum: 1 |
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maximum: 8 |
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dma-requests: |
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minimum: 1 |
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maximum: 16 |
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dma-masters: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: | |
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Number of DMA masters supported by the controller. In case if |
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not specified the driver will try to auto-detect this and |
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the rest of the optional parameters. |
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minimum: 1 |
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maximum: 4 |
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chan_allocation_order: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: | |
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DMA channels allocation order specifier. Zero means ascending order |
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(first free allocated), while one - descending (last free allocated). |
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default: 0 |
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enum: [0, 1] |
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chan_priority: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: | |
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DMA channels priority order. Zero means ascending channels priority |
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so the very first channel has the highest priority. While 1 means |
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descending priority (the last channel has the highest priority). |
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default: 0 |
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enum: [0, 1] |
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block_size: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: Maximum block size supported by the DMA controller. |
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enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095] |
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data-width: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: Data bus width per each DMA master in bytes. |
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items: |
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maxItems: 4 |
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items: |
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enum: [4, 8, 16, 32] |
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data_width: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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deprecated: true |
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description: | |
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Data bus width per each DMA master in (2^n * 8) bits. This property is |
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deprecated. It' usage is discouraged in favor of data-width one. Moreover |
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the property incorrectly permits to define data-bus width of 8 and 16 |
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bits, which is impossible in accordance with DW DMAC IP-core data book. |
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items: |
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maxItems: 4 |
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items: |
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enum: |
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- 0 # 8 bits |
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- 1 # 16 bits |
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- 2 # 32 bits |
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- 3 # 64 bits |
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- 4 # 128 bits |
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- 5 # 256 bits |
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default: 0 |
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multi-block: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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LLP-based multi-block transfer supported by hardware per |
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each DMA channel. |
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items: |
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maxItems: 8 |
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items: |
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enum: [0, 1] |
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default: 1 |
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snps,max-burst-len: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Maximum length of the burst transactions supported by the controller. |
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This property defines the upper limit of the run-time burst setting |
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(CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length |
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will be from 1 to max-burst-len words. It's an array property with one |
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cell per channel in the units determined by the value set in the |
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CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width). |
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items: |
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maxItems: 8 |
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items: |
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enum: [4, 8, 16, 32, 64, 128, 256] |
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default: 256 |
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snps,dma-protection-control: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: | |
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Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting |
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indicates the following features: bit 0 - privileged mode, |
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bit 1 - DMA is bufferable, bit 2 - DMA is cacheable. |
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default: 0 |
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minimum: 0 |
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maximum: 7 |
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unevaluatedProperties: false |
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required: |
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- compatible |
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- "#dma-cells" |
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- reg |
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- interrupts |
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examples: |
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- | |
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dma-controller@fc000000 { |
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compatible = "snps,dma-spear1340"; |
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reg = <0xfc000000 0x1000>; |
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interrupt-parent = <&vic1>; |
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interrupts = <12>; |
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dma-channels = <8>; |
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dma-requests = <16>; |
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dma-masters = <4>; |
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#dma-cells = <3>; |
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chan_allocation_order = <1>; |
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chan_priority = <1>; |
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block_size = <0xfff>; |
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data-width = <8 8>; |
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multi-block = <0 0 0 0 0 0 0 0>; |
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snps,max-burst-len = <16 16 4 4 4 4 4 4>; |
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}; |
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...
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