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171 lines
4.8 KiB
171 lines
4.8 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Renesas R-Car and RZ/G DMA Controller |
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maintainers: |
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- Yoshihiro Shimoda <[email protected]> |
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allOf: |
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- $ref: "dma-controller.yaml#" |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- renesas,dmac-r8a7742 # RZ/G1H |
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- renesas,dmac-r8a7743 # RZ/G1M |
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- renesas,dmac-r8a7744 # RZ/G1N |
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- renesas,dmac-r8a7745 # RZ/G1E |
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- renesas,dmac-r8a77470 # RZ/G1C |
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- renesas,dmac-r8a774a1 # RZ/G2M |
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- renesas,dmac-r8a774b1 # RZ/G2N |
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- renesas,dmac-r8a774c0 # RZ/G2E |
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- renesas,dmac-r8a774e1 # RZ/G2H |
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- renesas,dmac-r8a7790 # R-Car H2 |
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- renesas,dmac-r8a7791 # R-Car M2-W |
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- renesas,dmac-r8a7792 # R-Car V2H |
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- renesas,dmac-r8a7793 # R-Car M2-N |
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- renesas,dmac-r8a7794 # R-Car E2 |
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- renesas,dmac-r8a7795 # R-Car H3 |
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- renesas,dmac-r8a7796 # R-Car M3-W |
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- renesas,dmac-r8a77961 # R-Car M3-W+ |
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- renesas,dmac-r8a77965 # R-Car M3-N |
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- renesas,dmac-r8a77970 # R-Car V3M |
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- renesas,dmac-r8a77980 # R-Car V3H |
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- renesas,dmac-r8a77990 # R-Car E3 |
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- renesas,dmac-r8a77995 # R-Car D3 |
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- const: renesas,rcar-dmac |
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- items: |
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- const: renesas,dmac-r8a779a0 # R-Car V3U |
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reg: true |
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interrupts: |
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minItems: 9 |
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maxItems: 17 |
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interrupt-names: |
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minItems: 9 |
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maxItems: 17 |
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items: |
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- const: error |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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- pattern: "^ch([0-9]|1[0-5])$" |
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clocks: |
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maxItems: 1 |
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clock-names: |
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items: |
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- const: fck |
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'#dma-cells': |
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const: 1 |
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description: |
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The cell specifies the MID/RID of the DMAC port connected to |
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the DMA client. |
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dma-channels: |
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minimum: 8 |
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maximum: 16 |
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dma-channel-mask: true |
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iommus: |
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minItems: 8 |
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maxItems: 16 |
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power-domains: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- interrupt-names |
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- clocks |
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- clock-names |
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- '#dma-cells' |
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- dma-channels |
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- power-domains |
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- resets |
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if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- renesas,dmac-r8a779a0 |
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then: |
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properties: |
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reg: |
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items: |
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- description: Base register block |
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- description: Channel register block |
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else: |
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properties: |
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reg: |
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maxItems: 1 |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/r8a7790-cpg-mssr.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/r8a7790-sysc.h> |
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dmac0: dma-controller@e6700000 { |
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compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac"; |
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reg = <0xe6700000 0x20000>; |
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "error", |
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"ch0", "ch1", "ch2", "ch3", |
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"ch4", "ch5", "ch6", "ch7", |
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"ch8", "ch9", "ch10", "ch11", |
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"ch12", "ch13", "ch14"; |
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clocks = <&cpg CPG_MOD 219>; |
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clock-names = "fck"; |
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; |
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resets = <&cpg 219>; |
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#dma-cells = <1>; |
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dma-channels = <15>; |
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};
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