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116 lines
2.7 KiB
116 lines
2.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/intel,ldma.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Lightning Mountain centralized DMA controllers. |
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maintainers: |
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- [email protected] |
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- [email protected] |
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allOf: |
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- $ref: "dma-controller.yaml#" |
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properties: |
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compatible: |
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enum: |
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- intel,lgm-cdma |
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- intel,lgm-dma2tx |
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- intel,lgm-dma1rx |
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- intel,lgm-dma1tx |
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- intel,lgm-dma0tx |
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- intel,lgm-dma3 |
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- intel,lgm-toe-dma30 |
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- intel,lgm-toe-dma31 |
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reg: |
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maxItems: 1 |
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"#dma-cells": |
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const: 3 |
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description: |
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The first cell is the peripheral's DMA request line. |
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The second cell is the peripheral's (port) number corresponding to the channel. |
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The third cell is the burst length of the channel. |
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dma-channels: |
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minimum: 1 |
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maximum: 16 |
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dma-channel-mask: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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resets: |
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maxItems: 1 |
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reset-names: |
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items: |
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- const: ctrl |
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interrupts: |
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maxItems: 1 |
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intel,dma-poll-cnt: |
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$ref: /schemas/types.yaml#/definitions/uint32 |
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description: |
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DMA descriptor polling counter is used to control the poling mechanism |
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for the descriptor fetching for all channels. |
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intel,dma-byte-en: |
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type: boolean |
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description: |
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DMA byte enable is only valid for DMA write(RX). |
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Byte enable(1) means DMA write will be based on the number of dwords |
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instead of the whole burst. |
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intel,dma-drb: |
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type: boolean |
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description: |
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DMA descriptor read back to make sure data and desc synchronization. |
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intel,dma-dburst-wr: |
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type: boolean |
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description: |
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Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst; |
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if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16. |
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It only applies to RX DMA and memcopy DMA. |
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required: |
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- compatible |
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- reg |
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additionalProperties: false |
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examples: |
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- | |
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dma0: dma-controller@e0e00000 { |
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compatible = "intel,lgm-cdma"; |
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reg = <0xe0e00000 0x1000>; |
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#dma-cells = <3>; |
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dma-channels = <16>; |
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dma-channel-mask = <0xFFFF>; |
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interrupt-parent = <&ioapic1>; |
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interrupts = <82 1>; |
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resets = <&rcu0 0x30 0>; |
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reset-names = "ctrl"; |
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clocks = <&cgu0 80>; |
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intel,dma-poll-cnt = <4>; |
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intel,dma-byte-en; |
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intel,dma-drb; |
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}; |
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- | |
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dma3: dma-controller@ec800000 { |
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compatible = "intel,lgm-dma3"; |
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reg = <0xec800000 0x1000>; |
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clocks = <&cgu0 71>; |
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resets = <&rcu0 0x10 9>; |
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#dma-cells = <3>; |
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intel,dma-poll-cnt = <16>; |
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intel,dma-byte-en; |
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intel,dma-dburst-wr; |
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};
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