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117 lines
3.1 KiB
117 lines
3.1 KiB
* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX |
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Required properties: |
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- compatible : Should be one of |
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"fsl,imx25-sdma" |
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"fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" |
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"fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" |
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"fsl,imx51-sdma" |
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"fsl,imx53-sdma" |
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"fsl,imx6q-sdma" |
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"fsl,imx7d-sdma" |
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"fsl,imx8mq-sdma" |
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"fsl,imx8mm-sdma" |
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"fsl,imx8mn-sdma" |
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"fsl,imx8mp-sdma" |
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The -to variants should be preferred since they allow to determine the |
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correct ROM script addresses needed for the driver to work without additional |
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firmware. |
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- reg : Should contain SDMA registers location and length |
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- interrupts : Should contain SDMA interrupt |
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- #dma-cells : Must be <3>. |
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The first cell specifies the DMA request/event ID. See details below |
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about the second and third cell. |
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- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM |
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scripts firmware |
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The second cell of dma phandle specifies the peripheral type of DMA transfer. |
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The full ID of peripheral types can be found below. |
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ID transfer type |
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--------------------- |
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0 MCU domain SSI |
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1 Shared SSI |
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2 MMC |
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3 SDHC |
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4 MCU domain UART |
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5 Shared UART |
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6 FIRI |
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7 MCU domain CSPI |
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8 Shared CSPI |
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9 SIM |
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10 ATA |
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11 CCM |
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12 External peripheral |
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13 Memory Stick Host Controller |
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14 Shared Memory Stick Host Controller |
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15 DSP |
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16 Memory |
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17 FIFO type Memory |
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18 SPDIF |
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19 IPU Memory |
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20 ASRC |
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21 ESAI |
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22 SSI Dual FIFO (needs firmware ver >= 2) |
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23 Shared ASRC |
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24 SAI |
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The third cell specifies the transfer priority as below. |
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ID transfer priority |
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------------------------- |
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0 High |
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1 Medium |
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2 Low |
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Optional properties: |
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- gpr : The phandle to the General Purpose Register (GPR) node. |
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- fsl,sdma-event-remap : Register bits of sdma event remap, the format is |
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<reg shift val>. |
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reg is the GPR register offset. |
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shift is the bit position inside the GPR register. |
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val is the value of the bit (0 or 1). |
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Examples: |
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sdma@83fb0000 { |
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compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; |
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reg = <0x83fb0000 0x4000>; |
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interrupts = <6>; |
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#dma-cells = <3>; |
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fsl,sdma-ram-script-name = "sdma-imx51.bin"; |
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}; |
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DMA clients connected to the i.MX SDMA controller must use the format |
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described in the dma.txt file. |
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Examples: |
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ssi2: ssi@70014000 { |
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; |
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reg = <0x70014000 0x4000>; |
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interrupts = <30>; |
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clocks = <&clks 49>; |
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dmas = <&sdma 24 1 0>, |
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<&sdma 25 1 0>; |
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dma-names = "rx", "tx"; |
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fsl,fifo-depth = <15>; |
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}; |
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Using the fsl,sdma-event-remap property: |
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If we want to use SDMA on the SAI1 port on a MX6SX: |
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&sdma { |
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gpr = <&gpr>; |
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/* SDMA events remap for SAI1_RX and SAI1_TX */ |
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fsl,sdma-event-remap = <0 15 1>, <0 16 1>; |
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}; |
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The fsl,sdma-event-remap property in this case has two values: |
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- <0 15 1> means that the offset is 0, so GPR0 is the register of the |
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SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. |
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Setting bit 15 to 1 selects SAI1_RX. |
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- <0 16 1> means that the offset is 0, so GPR0 is the register of the |
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SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. |
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Setting bit 16 to 1 selects SAI1_TX.
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