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74 lines
1.8 KiB
74 lines
1.8 KiB
Texas Instruments DRA7x Display Subsystem |
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========================================= |
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See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic |
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description about OMAP Display Subsystem bindings. |
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DSS Core |
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-------- |
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Required properties: |
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- compatible: "ti,dra7-dss" |
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- reg: address and length of the register spaces for 'dss' |
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- ti,hwmods: "dss_core" |
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- clocks: handle to fclk |
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- clock-names: "fck" |
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- syscon: phandle to control module core syscon node |
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Optional properties: |
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Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties |
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can be used to describe the video PLLs: |
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- reg: address and length of the register spaces for 'pll1_clkctrl', |
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'pll1', 'pll2_clkctrl', 'pll2' |
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- clocks: handle to video1 pll clock and video2 pll clock |
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- clock-names: "video1_clk" and "video2_clk" |
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Required nodes: |
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- DISPC |
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Optional nodes: |
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- DSS Submodules: HDMI |
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- Video port for DPI output |
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DPI Endpoint required properties: |
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- data-lines: number of lines used |
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DISPC |
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----- |
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Required properties: |
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- compatible: "ti,dra7-dispc" |
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- reg: address and length of the register space |
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- ti,hwmods: "dss_dispc" |
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- interrupts: the DISPC interrupt |
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- clocks: handle to fclk |
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- clock-names: "fck" |
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Optional properties: |
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- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit |
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in bytes per second |
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HDMI |
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---- |
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Required properties: |
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- compatible: "ti,dra7-hdmi" |
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- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy', |
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'core' |
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- reg-names: "wp", "pll", "phy", "core" |
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- interrupts: the HDMI interrupt line |
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- ti,hwmods: "dss_hdmi" |
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- vdda-supply: vdda power supply |
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- clocks: handles to fclk and pll clock |
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- clock-names: "fck", "sys_clk" |
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Optional nodes: |
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- Video port for HDMI output |
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HDMI Endpoint optional properties: |
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- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-, |
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D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)
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