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241 lines
8.5 KiB
241 lines
8.5 KiB
STMicroelectronics stih4xx platforms |
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- sti-vtg: video timing generator |
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Required properties: |
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- compatible: "st,vtg" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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Optional properties: |
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- interrupts : VTG interrupt number to the CPU. |
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- st,slave: phandle on a slave vtg |
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- sti-vtac: video timing advanced inter dye communication Rx and TX |
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Required properties: |
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- compatible: "st,vtac-main" or "st,vtac-aux" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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- sti-display-subsystem: Master device for DRM sub-components |
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This device must be the parent of all the sub-components and is responsible |
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of bind them. |
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Required properties: |
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- compatible: "st,sti-display-subsystem" |
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- ranges: to allow probing of subdevices |
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- sti-compositor: frame compositor engine |
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must be a child of sti-display-subsystem |
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Required properties: |
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- compatible: "st,stih<chip>-compositor" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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- resets: resets to be used by the device |
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See ../reset/reset.txt for details. |
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- reset-names: names of the resets listed in resets property in the same |
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order. |
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- st,vtg: phandle(s) on vtg device (main and aux) nodes. |
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- sti-tvout: video out hardware block |
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must be a child of sti-display-subsystem |
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Required properties: |
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- compatible: "st,stih<chip>-tvout" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- reg-names: names of the mapped memory regions listed in regs property in |
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the same order. |
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- resets: resets to be used by the device |
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See ../reset/reset.txt for details. |
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- reset-names: names of the resets listed in resets property in the same |
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order. |
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- sti-hdmi: hdmi output block |
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must be a child of sti-display-subsystem |
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Required properties: |
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- compatible: "st,stih<chip>-hdmi"; |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- reg-names: names of the mapped memory regions listed in regs property in |
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the same order. |
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- interrupts : HDMI interrupt number to the CPU. |
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- interrupt-names: names of the interrupts listed in interrupts property in |
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the same order |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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- ddc: phandle of an I2C controller used for DDC EDID probing |
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sti-hda: |
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Required properties: |
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must be a child of sti-display-subsystem |
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- compatible: "st,stih<chip>-hda" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- reg-names: names of the mapped memory regions listed in regs property in |
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the same order. |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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sti-dvo: |
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Required properties: |
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must be a child of sti-display-subsystem |
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- compatible: "st,stih<chip>-dvo" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- reg-names: names of the mapped memory regions listed in regs property in |
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the same order. |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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- pinctrl-0: pin control handle |
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- pinctrl-names: names of the pin control states to use |
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- sti,panel: phandle of the panel connected to the DVO output |
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sti-hqvdp: |
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must be a child of sti-display-subsystem |
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Required properties: |
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- compatible: "st,stih<chip>-hqvdp" |
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- reg: Physical base address of the IP registers and length of memory mapped region. |
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- clocks: from common clock binding: handle hardware IP needed clocks, the |
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number of clocks may depend of the SoC type. |
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See ../clocks/clock-bindings.txt for details. |
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- clock-names: names of the clocks listed in clocks property in the same |
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order. |
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- resets: resets to be used by the device |
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See ../reset/reset.txt for details. |
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- reset-names: names of the resets listed in resets property in the same |
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order. |
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- st,vtg: phandle on vtg main device node. |
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Example: |
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/ { |
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... |
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vtg_main_slave: sti-vtg-main-slave@fe85a800 { |
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compatible = "st,vtg"; |
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reg = <0xfe85A800 0x300>; |
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interrupts = <GIC_SPI 175 IRQ_TYPE_NONE>; |
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}; |
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vtg_main: sti-vtg-main-master@fd348000 { |
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compatible = "st,vtg"; |
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reg = <0xfd348000 0x400>; |
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st,slave = <&vtg_main_slave>; |
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}; |
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vtg_aux_slave: sti-vtg-aux-slave@fd348400 { |
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compatible = "st,vtg"; |
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reg = <0xfe858200 0x300>; |
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interrupts = <GIC_SPI 176 IRQ_TYPE_NONE>; |
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}; |
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vtg_aux: sti-vtg-aux-master@fd348400 { |
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compatible = "st,vtg"; |
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reg = <0xfd348400 0x400>; |
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st,slave = <&vtg_aux_slave>; |
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}; |
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sti-vtac-rx-main@fee82800 { |
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compatible = "st,vtac-main"; |
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reg = <0xfee82800 0x200>; |
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clock-names = "vtac"; |
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clocks = <&clk_m_a2_div0 CLK_M_VTAC_MAIN_PHY>; |
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}; |
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sti-vtac-rx-aux@fee82a00 { |
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compatible = "st,vtac-aux"; |
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reg = <0xfee82a00 0x200>; |
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clock-names = "vtac"; |
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clocks = <&clk_m_a2_div0 CLK_M_VTAC_AUX_PHY>; |
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}; |
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sti-vtac-tx-main@fd349000 { |
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compatible = "st,vtac-main"; |
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reg = <0xfd349000 0x200>, <0xfd320000 0x10000>; |
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clock-names = "vtac"; |
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clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; |
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}; |
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sti-vtac-tx-aux@fd349200 { |
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compatible = "st,vtac-aux"; |
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reg = <0xfd349200 0x200>, <0xfd320000 0x10000>; |
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clock-names = "vtac"; |
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clocks = <&clk_s_a1_hs CLK_S_VTAC_TX_PHY>; |
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}; |
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sti-display-subsystem { |
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compatible = "st,sti-display-subsystem"; |
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ranges; |
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sti-compositor@fd340000 { |
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compatible = "st,stih416-compositor"; |
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reg = <0xfd340000 0x1000>; |
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clock-names = "compo_main", "compo_aux", |
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"pix_main", "pix_aux"; |
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clocks = <&clk_m_a2_div1 CLK_M_COMPO_MAIN>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>, |
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<&clockgen_c_vcc CLK_S_PIX_MAIN>, <&clockgen_c_vcc CLK_S_PIX_AUX>; |
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reset-names = "compo-main", "compo-aux"; |
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resets = <&softreset STIH416_COMPO_M_SOFTRESET>, <&softreset STIH416_COMPO_A_SOFTRESET>; |
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st,vtg = <&vtg_main>, <&vtg_aux>; |
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}; |
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sti-tvout@fe000000 { |
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compatible = "st,stih416-tvout"; |
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reg = <0xfe000000 0x1000>, <0xfe85a000 0x400>, <0xfe830000 0x10000>; |
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reg-names = "tvout-reg", "hda-reg", "syscfg"; |
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reset-names = "tvout"; |
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resets = <&softreset STIH416_HDTVOUT_SOFTRESET>; |
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}; |
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sti-hdmi@fe85c000 { |
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compatible = "st,stih416-hdmi"; |
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reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>; |
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reg-names = "hdmi-reg", "syscfg"; |
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interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>; |
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interrupt-names = "irq"; |
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clock-names = "pix", "tmds", "phy", "audio"; |
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clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; |
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}; |
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sti-hda@fe85a000 { |
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compatible = "st,stih416-hda"; |
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reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>; |
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reg-names = "hda-reg", "video-dacs-ctrl"; |
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clock-names = "pix", "hddac"; |
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clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; |
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}; |
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sti-dvo@8d00400 { |
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compatible = "st,stih407-dvo"; |
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reg = <0x8d00400 0x200>; |
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reg-names = "dvo-reg"; |
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clock-names = "dvo_pix", "dvo", |
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"main_parent", "aux_parent"; |
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clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>, |
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<&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_dvo>; |
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sti,panel = <&panel_dvo>; |
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}; |
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sti-hqvdp@9c000000 { |
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compatible = "st,stih407-hqvdp"; |
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reg = <0x9C00000 0x100000>; |
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clock-names = "hqvdp", "pix_main"; |
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clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; |
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reset-names = "hqvdp"; |
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resets = <&softreset STIH407_HDQVDP_SOFTRESET>; |
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st,vtg = <&vtg_main>; |
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}; |
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}; |
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... |
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};
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