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148 lines
3.9 KiB
148 lines
3.9 KiB
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
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# Copyright 2019 BayLibre, SAS |
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%YAML 1.2 |
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--- |
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$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#" |
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$schema: "http://devicetree.org/meta-schemas/core.yaml#" |
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title: Amlogic specific extensions to the Synopsys Designware HDMI Controller |
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maintainers: |
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- Neil Armstrong <[email protected]> |
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description: | |
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The Amlogic Meson Synopsys Designware Integration is composed of |
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- A Synopsys DesignWare HDMI Controller IP |
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- A TOP control block controlling the Clocks and PHY |
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- A custom HDMI PHY in order to convert video to TMDS signal |
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___________________________________ |
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| HDMI TOP |<= HPD |
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|___________________________________| |
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| | | |
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| Synopsys HDMI | HDMI PHY |=> TMDS |
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| Controller |________________| |
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|___________________________________|<=> DDC |
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The HDMI TOP block only supports HPD sensing. |
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The Synopsys HDMI Controller interrupt is routed through the |
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TOP Block interrupt. |
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Communication to the TOP Block and the Synopsys HDMI Controller is done |
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via a pair of dedicated addr+read/write registers. |
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The HDMI PHY is configured by registers in the HHI register block. |
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Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux |
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selects either the ENCI encoder for the 576i or 480i formats or the ENCP |
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encoder for all the other formats including interlaced HD formats. |
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The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate |
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DVI timings for the HDMI controller. |
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Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare |
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HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF |
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audio source interfaces. |
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properties: |
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compatible: |
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oneOf: |
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- items: |
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- enum: |
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- amlogic,meson-gxbb-dw-hdmi # GXBB (S905) |
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- amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D) |
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- amlogic,meson-gxm-dw-hdmi # GXM (S912) |
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- const: amlogic,meson-gx-dw-hdmi |
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- enum: |
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- amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2) |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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minItems: 3 |
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clock-names: |
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items: |
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- const: isfr |
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- const: iahb |
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- const: venci |
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resets: |
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minItems: 3 |
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reset-names: |
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items: |
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- const: hdmitx_apb |
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- const: hdmitx |
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- const: hdmitx_phy |
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hdmi-supply: |
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description: phandle to an external 5V regulator to power the HDMI logic |
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port@0: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: |
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A port node pointing to the VENC Input port node. |
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port@1: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: |
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A port node pointing to the TMDS Output port node. |
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"#address-cells": |
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const: 1 |
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"#size-cells": |
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const: 0 |
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"#sound-dai-cells": |
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const: 0 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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- resets |
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- reset-names |
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- port@0 |
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- port@1 |
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- "#address-cells" |
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- "#size-cells" |
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additionalProperties: false |
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examples: |
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- | |
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hdmi_tx: hdmi-tx@c883a000 { |
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compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; |
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reg = <0xc883a000 0x1c>; |
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interrupts = <57>; |
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resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>; |
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reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; |
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clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>; |
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clock-names = "isfr", "iahb", "venci"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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/* VPU VENC Input */ |
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hdmi_tx_venc_port: port@0 { |
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reg = <0>; |
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hdmi_tx_in: endpoint { |
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remote-endpoint = <&hdmi_tx_out>; |
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}; |
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}; |
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/* TMDS Output */ |
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hdmi_tx_tmds_port: port@1 { |
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reg = <1>; |
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hdmi_tx_tmds_out: endpoint { |
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remote-endpoint = <&hdmi_connector_in>; |
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}; |
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}; |
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}; |
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