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260 lines
5.8 KiB
260 lines
5.8 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings |
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description: | |
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The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller |
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IP with Allwinner\'s own PHY IP. It supports audio and video outputs |
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and CEC. |
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These DT bindings follow the Synopsys DWC HDMI TX bindings defined |
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in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with |
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the following device-specific properties. |
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maintainers: |
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- Chen-Yu Tsai <[email protected]> |
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- Maxime Ripard <[email protected]> |
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properties: |
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"#phy-cells": |
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const: 0 |
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compatible: |
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oneOf: |
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- const: allwinner,sun8i-a83t-dw-hdmi |
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- const: allwinner,sun50i-h6-dw-hdmi |
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- items: |
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- enum: |
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- allwinner,sun8i-h3-dw-hdmi |
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- allwinner,sun8i-r40-dw-hdmi |
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- allwinner,sun50i-a64-dw-hdmi |
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- const: allwinner,sun8i-a83t-dw-hdmi |
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reg: |
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maxItems: 1 |
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reg-io-width: |
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const: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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minItems: 3 |
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maxItems: 6 |
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items: |
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- description: Bus Clock |
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- description: Register Clock |
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- description: TMDS Clock |
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- description: HDMI CEC Clock |
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- description: HDCP Clock |
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- description: HDCP Bus Clock |
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clock-names: |
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minItems: 3 |
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maxItems: 6 |
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items: |
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- const: iahb |
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- const: isfr |
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- const: tmds |
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- const: cec |
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- const: hdcp |
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- const: hdcp-bus |
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resets: |
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minItems: 1 |
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maxItems: 2 |
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items: |
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- description: HDMI Controller Reset |
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- description: HDCP Reset |
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reset-names: |
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minItems: 1 |
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maxItems: 2 |
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items: |
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- const: ctrl |
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- const: hdcp |
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phys: |
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maxItems: 1 |
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description: |
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Phandle to the DWC HDMI PHY. |
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phy-names: |
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const: phy |
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hvcc-supply: |
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description: |
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The VCC power supply of the controller |
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ports: |
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$ref: /schemas/graph.yaml#/properties/ports |
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properties: |
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port@0: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: | |
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Input endpoints of the controller. Usually the associated |
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TCON. |
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port@1: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: | |
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Output endpoints of the controller. Usually an HDMI |
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connector. |
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required: |
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- port@0 |
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- port@1 |
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required: |
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- compatible |
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- reg |
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- reg-io-width |
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- interrupts |
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- clocks |
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- clock-names |
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- resets |
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- reset-names |
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- phys |
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- phy-names |
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- ports |
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if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- allwinner,sun50i-h6-dw-hdmi |
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then: |
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properties: |
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clocks: |
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minItems: 6 |
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clock-names: |
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minItems: 6 |
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resets: |
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minItems: 2 |
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reset-names: |
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minItems: 2 |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/* |
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* This comes from the clock/sun8i-a83t-ccu.h and |
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* reset/sun8i-a83t-ccu.h headers, but we can't include them since |
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* it would trigger a bunch of warnings for redefinitions of |
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* symbols with the other example. |
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*/ |
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#define CLK_BUS_HDMI 39 |
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#define CLK_HDMI 93 |
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#define CLK_HDMI_SLOW 94 |
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#define RST_BUS_HDMI1 26 |
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hdmi@1ee0000 { |
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compatible = "allwinner,sun8i-a83t-dw-hdmi"; |
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reg = <0x01ee0000 0x10000>; |
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reg-io-width = <1>; |
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, |
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<&ccu CLK_HDMI>; |
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clock-names = "iahb", "isfr", "tmds"; |
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resets = <&ccu RST_BUS_HDMI1>; |
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reset-names = "ctrl"; |
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phys = <&hdmi_phy>; |
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phy-names = "phy"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&hdmi_pins>; |
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status = "disabled"; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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endpoint { |
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remote-endpoint = <&tcon1_out_hdmi>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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}; |
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}; |
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}; |
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/* Cleanup after ourselves */ |
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#undef CLK_BUS_HDMI |
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#undef CLK_HDMI |
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#undef CLK_HDMI_SLOW |
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- | |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/* |
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* This comes from the clock/sun50i-h6-ccu.h and |
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* reset/sun50i-h6-ccu.h headers, but we can't include them since |
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* it would trigger a bunch of warnings for redefinitions of |
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* symbols with the other example. |
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*/ |
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#define CLK_BUS_HDMI 126 |
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#define CLK_BUS_HDCP 137 |
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#define CLK_HDMI 123 |
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#define CLK_HDMI_SLOW 124 |
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#define CLK_HDMI_CEC 125 |
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#define CLK_HDCP 136 |
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#define RST_BUS_HDMI_SUB 57 |
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#define RST_BUS_HDCP 62 |
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hdmi@6000000 { |
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compatible = "allwinner,sun50i-h6-dw-hdmi"; |
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reg = <0x06000000 0x10000>; |
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reg-io-width = <1>; |
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, |
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<&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, |
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<&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; |
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clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", |
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"hdcp-bus"; |
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resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; |
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reset-names = "ctrl", "hdcp"; |
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phys = <&hdmi_phy>; |
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phy-names = "phy"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&hdmi_pins>; |
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status = "disabled"; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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endpoint { |
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remote-endpoint = <&tcon_top_hdmi_out_hdmi>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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}; |
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}; |
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}; |
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...
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