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125 lines
2.9 KiB
125 lines
2.9 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-frontend.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Allwinner A10 Display Engine Frontend Device Tree Bindings |
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maintainers: |
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- Chen-Yu Tsai <[email protected]> |
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- Maxime Ripard <[email protected]> |
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description: | |
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The display engine frontend does formats conversion, scaling, |
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deinterlacing and color space conversion. |
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properties: |
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compatible: |
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enum: |
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- allwinner,sun4i-a10-display-frontend |
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- allwinner,sun5i-a13-display-frontend |
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- allwinner,sun6i-a31-display-frontend |
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- allwinner,sun7i-a20-display-frontend |
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- allwinner,sun8i-a23-display-frontend |
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- allwinner,sun8i-a33-display-frontend |
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- allwinner,sun9i-a80-display-frontend |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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items: |
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- description: The frontend interface clock |
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- description: The frontend module clock |
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- description: The frontend DRAM clock |
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clock-names: |
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items: |
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- const: ahb |
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- const: mod |
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- const: ram |
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# FIXME: This should be made required eventually once every SoC will |
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# have the MBUS declared. |
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interconnects: |
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maxItems: 1 |
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# FIXME: This should be made required eventually once every SoC will |
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# have the MBUS declared. |
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interconnect-names: |
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const: dma-mem |
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resets: |
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maxItems: 1 |
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ports: |
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$ref: /schemas/graph.yaml#/properties/ports |
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properties: |
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port@0: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: | |
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Input endpoints of the controller. |
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port@1: |
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$ref: /schemas/graph.yaml#/properties/port |
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description: | |
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Output endpoints of the controller. |
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required: |
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- port@1 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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- resets |
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- ports |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/sun4i-a10-ccu.h> |
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#include <dt-bindings/reset/sun4i-a10-ccu.h> |
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fe0: display-frontend@1e00000 { |
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compatible = "allwinner,sun4i-a10-display-frontend"; |
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reg = <0x01e00000 0x20000>; |
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interrupts = <47>; |
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clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>, |
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<&ccu CLK_DRAM_DE_FE0>; |
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clock-names = "ahb", "mod", |
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"ram"; |
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resets = <&ccu RST_DE_FE0>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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fe0_out: port@1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <1>; |
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fe0_out_be0: endpoint@0 { |
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reg = <0>; |
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remote-endpoint = <&be0_in_fe0>; |
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}; |
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fe0_out_be1: endpoint@1 { |
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reg = <1>; |
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remote-endpoint = <&be1_in_fe0>; |
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}; |
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}; |
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}; |
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}; |
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...
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